Radiant energy – Irradiation of objects or material – Irradiation of semiconductor devices
Reexamination Certificate
2002-12-17
2004-09-07
Lee, John R. (Department: 2881)
Radiant energy
Irradiation of objects or material
Irradiation of semiconductor devices
Reexamination Certificate
active
06787783
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor chip repair and editing, and in particular, to apparatus and processes for editing and repairing integrated circuits having copper and/or organic-based features.
2. Description of Related Art
Present processes for integrated circuit (IC) repair and editing primarily rely on the use of focused ion beams for spatially localized removal and deposition of materials. These beams are generated by a Focused Ion Beam (FIB) tool which utilizes a liquid metal ion source, typically gallium (Ga+), from which highly energetic beams (E>30 keV) are formed and then focused onto the sample surface by electrostatic lenses. However, exposure to these highly energetic ion beams often causes IC damage, gallium contamination, and physical sputtering of the sample surface whereby the actual amount of material removed by such sputtering depends on the total ion dose and energy at each pixel location. Further, a significant amount of the sputtered material is undesirably re-deposited onto adjacent areas. This re-deposition slows the rate at which material can be removed, limits the maximum achievable aspect ratio of holes and openings created by FIB, and can adversely affect the electrical properties of the IC under edit.
Gas-assisted etching techniques, which involve ion beam induced chemical reactions, have been introduced in the art to overcome the problems associated with FIB tools by improving volatilization of these byproducts and thus avoid the undesired re-deposition onto adjacent areas of the sample surface. However, it has been found that gas-assisted etching cannot completely address these issues, due to the continued dependence of FIB on gallium ion based beams for inducing these reactions.
In recent years, the introduction of copper for interconnect metallization has presented additional problems in the processes of chip repair and editing using existing FIB tools and techniques, including those having g assisted etching (GAE) options. In the case of copper interconnect metalization editing, ion beam compatible gas chemistries have not been determined for complete volatilization of the etch products, which leads to re-deposition of conductive copper by-products onto adjacent areas and degradation of the IC's electrical performance. For example, non-volatility and subsequent re-deposition of undesired sputtered metal products on the sidewalls of a deep access hole opening created with FIB during high-aspect ratio repairs involving features down at the lower interconnect levels is shown in the prior art illustration of FIG.
1
.
As shown in
FIG. 1
, an energetic focused ion beam
1
creates a deep-hole
3
opening traversing through a plurality of interconnect levels
4
consisting of metal interconnects and electrically insulative inter-level dielectric (ILD) materials
10
in order to expose a particular metal interconnect feature of interest
5
at the bottom of the deep-hole. The energetic focused ion beam
1
is then focused into the deep-hole
3
so as to contact the metal feature
5
at the bottom of the opening in order to edit the desired interconnect feature without affecting adjacent inter-level dielectric (ILD) materials
10
. The IC interconnect is then cut by milling the metal feature (e.g. copper) with little chemical assistance, as there is currently no completely effective ion beam compatible chemistries for volatilization of the metal etch by-products, particularly in the case of copper. As such, these conductive by-products
7
from the FIB milling of the metal are then re-deposited on the surrounding sidewalls of the deep-hole possibly shorting all interconnect layers together. Additionally, the FIB milling process also damages ILD surface areas
9
of interconnect levels
4
on the top surface and along sidewalls within the deep-hole. Another common repair scenario involves clearing large surface areas of metal such as copper that normally have non-uniform removal rates, due to grain orientation dependencies of the ion-beam to sample surface interaction. Also commonly required is the removal of insulator (SiLK or Oxide) materials prior to accessing buried features. In IC editing, the challenge is to smoothly remove the upper layers, or in the case of ILD etching without inducing electrical leakage paths.
In semiconductor IC repair and editing, the limitations of FIB tools have become even more pronounced recently with the introduction of organic-based materials to form the interconnect level ILD layers
4
such as “Silicon Low-K,” otherwise known as SiLK™, a registered trademark of Dow Chemical Company. Electronic device damage, gallium contamination, and physical sputtering of the sample surface caused by exposure to the highly energetic ion beams of FIB are dramatically increased in those ICs having organic-based ILD materials as the electronic properties of such materials are dramatically altered by exposure to these highly energetic ion beams. The surface damage and subsequent electrical leakage of these normally very insulative organic ILD layers can result from merely imaging such layers with the FIB, as well as the ensuing milling process which typically brings orders of magnitude higher doses of energetic ions. Most IC damage manifests in the formation of graphitic surface layers which cause electrical conduction and leakage between metal features (either inter- or intra-level). Gas-assisted-etching (GAE) FIB techniques, which utilize ion beam induced chemistries, have been introduced to improve volatilization and removal of damaged ILD material. However, since both mechanical and chemical components are present in GAE FIB methods, there is still ion beam energetic damage to the ILD material.
Additionally, beam-induced deposition of metals for the intended electrical connection of IC features, without re-deposition or damage effects, remains important in chip repair. Beam-induced oxide deposition also remains important for the ability to passivate and subsequently isolate features electrically. Unfortunately, ion beam induced deposition of metals usually damages the underlying ILD layer, which defeats localization of the conductive feature that is desired, while beam-induced deposition of oxide layers (insulator layers) are typically rich in gallium ions, and as a result, exhibit poor electrical isolation in addition to possible induction of conductive organic ILD surfaces lying underneath the deposited oxide coating or mask.
Accordingly, as modern semiconductor technology continues to require smaller ICs having diminished feature sizes, conventional apparatus and techniques for repairing and editing ICs will no longer be reliable. In fact, smaller interconnect features are more easily cut, since there is less initial volume of material to remove. However, it is the increased packing IC densities which severely decrease the separation between features that must be isolated electrically. Accordingly, a need continues to exist in the art for providing improved apparatus and techniques that will be capable of repairing and editing future generations of ICs having reduced feature sizes and increased packing densities without the above disadvantages caused by lack of product volatility in metal etch reactions or energetic ion beam damage of ILD layers.
SUMMARY OF THE INVENTION
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide apparatus and techniques for integrated circuit chip repair that significantly minimize IC damage, electronic device damage, leakage between metal features, damage to ILD material, wafer contamination (gallium contamination) and physical sputtering of undesired material while still possessing nanometer-scale spatial resolution.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention, which, is directed to in a first aspect a method of editing an integrated circuit by prov
Marchman Herschel M.
Shore Aaron D.
Delio & Peterson LLC
International Business Machines - Corporation
Lee John R.
Reynolds Kelly M.
Smith, II Johnnie L.
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