Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2002-07-23
2003-12-16
Le, Thong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S189090, C365S207000
Reexamination Certificate
active
06665216
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to digital memory systems and, more particularly, to methods and systems for reading data stored in a memory cell.
2. Description of the Related Art
Memory systems typically include an array of separate memory cells. Each memory cell stores one data bit (i.e., a “1” or a “0” state). In an EPROM such as an EEPROM, a flash EPROM, or a flash EEPROM, the data stored in each memory cell must be verified. One method of verifying the contents of the data stored in each memory cell is to compare a cell output voltage of the memory cell to a reference output voltage of a reference cell. The reference cell voltage may be the equivalent of a “1” or a “0” state. The cell output voltage is compared to the reference output voltage. If the cell output voltage is the same as the reference output voltage, then the memory cell is verified as having the same state as the reference cell. The state of the memory cell is then compared to the data that is intended to be stored in the memory cell. If the memory cell has the correct state, then a next memory cell is similarly tested. If the memory cell does not have the correct state, then the memory cell must be reprogrammed.
One of the problems of the above process is that, as semiconductor device structures have become smaller, the speeds of the devices have increased, and the operating voltages have been reduced. For example, in many early generations of semiconductor devices, a “1” state was represented by a 5 VDC output voltage and a “0” state was represented by a 0 VDC (i.e., ground) output voltage. In more recent device structures a “1” state has been represented by a 1 VDC or even less (e.g., 0.6 VDC) output voltage, while a “0” state still has been represented by a 0 VDC (e.g., ground) output voltage. Further, the 0 VDC can often be slightly above ground potential such as 0.1 VDC. As the voltage difference between a “1” state and a “0” state has decreased, the process of determining whether a given device is in a “1” or “0” state becomes more finite and typically slower. The process has become more finite because the voltage difference is small (e.g., less than 1 VDC) and therefore requires very specific measurement. Because the process is more finite and because the voltage is so small, the process also has become slower. The output voltage typically must be allowed to rise to a near maximum voltage before the output voltage can be accurately measured.
FIG. 1
is a schematic diagram of a prior art circuit
100
for comparing a single reference cell
20
to a memory cell
10
. The memory cell
10
generates a memory cell current when a gate potential is applied to the memory cell's word line. The memory cell current is compared to a current from a reference cell
20
by the comparator
30
. Typically, EPROMs employ a column of UV-erased cells, which are identical in structure to the memory cells and act as the reference cells. The comparator
30
determines whether the memory cell
10
being verified is drawing more or less current than the reference cell
20
, which is weighted in some relationship to the memory cell
10
. In doing so, the comparator
30
verifies the program state of the memory cell
10
.
As both the memory cell
10
and the reference cell
20
of the typical EPROM are UV-erased, each has a different distribution of currents. Normally, this difference in distribution prevents the currents from being compared directly because of the possibility that an erased memory cell being verified could appear to be programmed and vice versa. To resolve this problem, a resistive load (such as R
ref
) is used to effectively divide or weight the reference current, I
ref
. The typical load used is one-half or one-third that of the load R
cel
for the memory cell
10
, resulting in a 2 to 1 or 3 to 1 load ratio. Currents also have been compared using other load ratios.
In
FIG. 1
, memory cell
10
is a transistor that represents a typical array memory cell such as in a “flash” EPROM. The memory cell
10
is coupled to a positive input
31
of comparator
30
via line
41
. A potential applied to the gate of memory cell
10
puts the cell into conduction, provided the potential is greater than the cell's threshold potential, V
t1(cel)
. Reference cell
20
is the reference cell for memory cell
10
and is used to produce a reference current, I
ref
, which is used to determine the presence of a charge in the memory cell
10
. The reference cell
20
is coupled to the negative input
32
of comparator
30
via line
42
. A potential applied to the gate of reference cell
20
puts the reference cell into conduction if the potential is greater than its threshold potential, V
t1(ref)
. When the program state of memory cell
10
is being verified, a gate potential, V
WL1(cel)
, is applied to the memory cell
10
and a gate potential, V
WL1(ref)
, is applied to reference cell
20
to produce a memory cell current, I
cel
, and a reference cell current, I
ref
, respectively. When currents I
cel
and I
ref
are conducting, array side load resistance R
cel
11
and reference cell side load resistance R
ref
21
create voltages V+ and V−, respectively. Voltages V+ and V− represent the input voltages to comparator
30
.
If both cells
10
and
20
are conducting, then the input voltages to comparator
30
are depicted by the following approximate or first order equations:
TABLE 1
V+ = I
cel
R
cel
= (½) beta (V
WL1(cel)
− V
t1(cel)
)R
cel
(1)
V− = I
ref
R
ref
= (½) beta (V
WL1(ref)
− V
t1(ref)
)R
ref
(2)
The output signal of the comparator
30
, CPout, changes state or “trips” when:
TABLE 2
V+ and V− are equal:
(V
W1(cel)
− V
t1(cel)
)R
(cel) = (V
WL1(ref)
− V
t1(ref)
)R
(ref)
(3)
As described above, the comparator
30
amplifies the difference between the V+ and V−. If the memory cell
10
is conducting and the reference cell
20
is not conducting, then the difference output from the comparator
30
can still be quite small and therefore slow to change state. As a result, verifying each of the many thousands of memory cells in an entire programmed memory array will require an excessive amount of time.
Therefore, in view of the foregoing, what is needed is a method and apparatus for quickly and accurately verifying the programmed state of each memory cell in a programmed memory array.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by using dual reference cells to read or verify data in a memory cell. By way of example, the present invention may be implemented in the form of a system, an apparatus, a method, a device, or a computer readable media.
In accordance with one aspect of the present invention, a system for reading data in a memory cell is provided. This system includes first, second, and third comparators, each of which has a first input and a second input. A first reference cell having a low reference voltage is coupled to the first input of the first comparator. A second reference cell having a high reference voltage is coupled to the first input of the second comparator. A memory cell having a memory cell voltage is coupled to the second input of both the first comparator and also the second comparator. The first input of the third comparator is coupled to an output signal of the first comparator, which includes a difference voltage between the memory cell voltage and the low reference voltage. The second input of the third comparator is coupled to an output signal of the second comparator, which includes a difference voltage between the memory cell voltage and the high reference voltage.
In one embodiment, the output signal of the third comparator is a representation of data stored in the memory cell. In one embodiment, the low reference voltage is substantially equal to the memory cell voltage when the memory cell is in a low voltage state. In one embodiment, the high
Chen Gin-Laing
Ho Hsin-Yi
Ho Wen-Chiao
Hung Chun-Hsiung
Kuo Nai-Ping
Le Thong
Macronix International Co. Ltd.
Martine & Penilla LLP
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