Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-12-02
2002-01-29
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C700S110000, C700S121000
Reexamination Certificate
active
06343370
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pattern distortion detecting apparatus and method for detecting a pattern distortion that may occur in pattern forming processes such as photolithography and etching used in semiconductor manufacture. More specifically, the invention relates to a pattern distortion detecting apparatus and method for detecting a portion where a pattern distortion out of an allowable range may occur by predicting patterns that will be formed in a semiconductor manufacturing process and by detecting differences between the predicted patterns and design layout patterns.
2. Background Art
At present, the design rules of semiconductor devices have reached the 0.2 &mgr;m level and this value is smaller than light source wavelengths (0.248 &mgr;m in the case of an excimer laser) of steppers for transfer of such patterns. Since the resolution performance deteriorates significantly in this circumstance, it is attempted to improve the resolution performance by using a special transfer technique such as a modified illumination technique.
Where the modified illumination is employed, the pattern fidelity deteriorates though the resolution performance is improved. This will be explained below with reference to
FIG. 16
, which shows an example of the optical proximity effect in pattern formation. More specifically,
FIG. 16
shows how a dimension of resist patterns that are formed by using a modified illumination technique varies as the distance between adjacent patterns, i.e. the pitch, is changed for design layout patterns whose line width is fixed at 0.25 &mgr;m.
As seen from
FIG. 16
, the resist dimension sharply varies when the pitch is changed in a range of 0.5-1.0 &mgr;m. Our experiments showed that the amount of this variation, which depends on the process conditions, is 0.05 &mgr;m at the maximum. Such a large variation amount is not allowable in view of the dimensional accuracy required in forming 0.25 &mgr;m devices is within ±0.03 &mgr;m.
Also in etching processes, variations in pattern dimensions may occur due to differences in the density of miniaturized patterns.
The pitch inspection technique is one of the techniques that have been developed to solve the above problem.
FIG. 17
shows an example of a pitch inspection method. In this pitch inspection method, patterns
161
-
164
having a particular line width L are extracted. Then, the sidelines
165
and
166
are extracted as a pair of side lines which has a particular distance S
2
among a combination of a sideline of one of the patterns
161
-
164
and a sideline of another pattern that is adjacent to the former sideline. With the pitch defined as the sum of the line width of a pattern and the distance between adjacent sidelines, this method enables recognition as to whether there exists a pattern having a particular line width and pitch. If a pattern having a particular line width and pitch is detected, the layout patterns are modified when necessary.
A problem of the above pitch inspection method will be described below with reference to FIG.
18
. According to the above method, the entirety of each of patterns
171
,
172
,
174
, and
175
and part of a pattern
173
are extracted as patterns having a particular line width L
1
. Then, among the sidelines of the extracted patterns, sidelines
176
,
177
, and
179
are extracted as sidelines having a particular value S
2
as a distance to the sideline of an adjacent pattern. However, among the extracted sidelines, the sideline
179
and a sideline
178
that is part of the sideline
176
are sidelines that should not be extracted. This is because a variation in pattern dimension as shown in
FIG. 16
exceeds the allowable range when only patterns of the same line width are arranged adjacent to each other, a dimensional variation larger than the allowable range does not necessarily occur when a pattern width is large as in the case of the sideline
178
. In the case of the sideline
179
of which opposite sideline is short, there does not occur a dimensional variation larger than the allowable range. The conventional pitch inspection method thus has a problem that it cannot avoid the above types of detection errors.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problems in the conventional art, and an object of the present invention is therefore to provide a pattern distortion detecting apparatus and method which can detect a pattern distortion with high accuracy without causing detection errors.
Another object of the present invention is to provide a pattern distortion detecting apparatus and method which can inspect the portions in remarkable variations of predicted finished pattern dimensions considering the variations of a plurality of optical conditions and a plurality of patterns forming process conditions.
A further object of the present invention is to provide a pattern distortion detecting apparatus and method which can detect a pattern distortion in an important part of a circuit with high accuracy, as well as being able to do the inspection considering, for example, a contrast of an optical intensity.
A further object of the present invention is to provide a pattern distortion detecting apparatus and method by which pattern distortion errors are obtained more accurately by generating a plurality of different predicted patterns according to different optical or process conditions and performing logical figure operation between these patterns and the design layout pattern reference layout pattern.
According to one aspect of the present invention, in a pattern distortion detecting method in a semiconductor manufacturing process, a predicted finished layout pattern is formed based on a design layout pattern or a inspection layout pattern. An outline or a outline of the predicted finished layout pattern is converted into a polygon to generate a polygonized predicted finished layout pattern. A pattern distortion in said predicted finished layout pattern is detected by logical figure operation of the input data of said polygonized predicted finished layout patterns only or of said polygonized predicted finished layout patterns and said design layout pattern or inspection layout pattern.
In the pattern distortion detecting method, the number of apices of the polygonized predicted finished layout pattern may be reduced.
In the pattern distortion detecting method, in the step of forming a test reference layout pattern, an upper limit test reference layout pattern for defining an allowable upper limit may be formed by enlarging the design layout pattern, and a lower limit test reference layout pattern for defining an allowable lower limit may be formed by reducing the design layout pattern.
In the pattern distortion detecting method, an amount of the pattern distortion may be calculated , where the pattern distortion is detected, based on a difference between the design layout pattern or a reference layout pattern and the predicted finished layout pattern.
In the pattern distortion detecting method, it may be detected whether the finished layout pattern shrinks or expands more than the design layout pattern by comparing the polygonized predicted finished layout pattern with the test reference layout pattern.
In the pattern distortion detecting method, a graphical operation may be performed between the pattern distortion of the predicted layout pattern and another design layout layer, and pattern distortion information may be selected based on a pattern distortion information selecting conditions.
In the pattern distortion detecting method, a plurality of predicted finished layout patterns may be formed based on a design layout pattern or a inspection layout pattern corresponding to a plurality of optical conditions and/or a plurality of pattern forming process conditions. Further, contrast information of the predicted finished pattern may be obtained based on a difference pattern between the plurality of predicted finished layout patterns.
In the pattern dis
Moriizumi Koichi
Taoka Hironobu
Kik Phallaka
Mitsubishi Denki Kabusiki Kaisha
Smith Matthew
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