Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-08
2003-02-18
Nelms, David (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06523156
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuit design. More specifically, the invention relates to mechanisms for timing optimization.
FIG. 1
illustrates a conventional integrated circuit design flow
100
. Initially, the circuit's behavior is described in a high level language in a design entry procedure
102
. Logic synthesis tools then transform the high level description into a listing of logic cells (logic netlist) and interconnection information in a synthesis procedure
104
. The logic cells correspond to cells within a standard cell library. In general terms, logic circuit synthesis generates an initial circuit topology that satisfies the basic logic requirements as defmed by the high level design description. The initial design can be presented graphically as a schematic and also in a data file listing the included logic elements and their interconnections. This data file is generally referred to as a netlist.
The timing optimization procedures (
106
,
110
, and
114
) are described further below, and a description of such optimization procedures is skipped for now so as to more clearly describe the other operations of the design flow. After synthesis, the cells listed in the layout netlist are obtained from the standard library and arranged within a design layout in a placement procedure
108
. The placed cells are then routed together in operation
112
. The cells are placed and routed together into a layout design that is equivalent to the original design description, as well as the layout design netlist. Said in another way, the layout netlist (and original high level description) is in effect transformed into a design layout having interconnected cells.
Logic synthesis tools map functional groups within the high level description to cells having the same logic function. The standard cell library typically provides a set of discrete implementations of each logic function. The different implementations of a particular logic function are designed to drive different capacitive loads while maintaining similar rise/fall times for multiples of a standard load, usually one, two, and four. Unfortunately, the different implementations typically have different associated delays.
As shown, timing optimization procedures are typically performed after the synthesis procedure
104
, after the placement procedure
108
, and after the routing procedure
112
. If timing requirements are not met in any of the timing optimization procedures (e.g.,
106
,
110
, or
114
), the entire design flow from timing synthesis
104
through timing optimization
114
are repeated. This reiteration of all or part of the design flow may occur numerous times until the timing goals are met. Unfortunately, these reiterations are usually associated with significant design time and costs.
The various optimization techniques operate on the netlist to attain a satisfactory balance between different requirements. Timing assurance especially depends on the process technology and placement of the circuit design. Timing assurance in synthesis has traditionally operated on a discrete set of cell types with a discrete set of drive capabilities. A static timing analysis-based tool is typically used to select among cells of different drive capabilities. Two important parameters that control this selection are the intrinsic load of the cells on the driver cell, which is well known, and also the load of the interconnect wires, which is not known until the final layout of the design and strongly depends on the placement and routing stages.
Wire load is often estimated in the absence of any placement and routing information. These estimates are typically done without any knowledge of the eventual placement of the logic design and, accordingly, deviate significantly from the actual loads. This creates what is called the “timing closure” problem where several iterations are done between the synthesis-based timing optimization and placement until timing constraints are satisfied. To compensate for the changes in the wire loads, the most common techniques include replacing an existing cell with one of higher drive but the same functionality, and duplicating a cell and splitting the original cell's load over the resulting pair.
The netlist changes as the load conditions change. These changes may require additional cells and the removal of other cells (e.g., if they are found to be redundant). One such change usually triggers more changes. There is only a discrete set of sizes available, and after replacement, signal delays through the cells are affected differently when they are replaced with other cells. Changes in sizing of replacement cells vs. replaced cells also impacts the delays of the cells'preceding driver cell(s) because of changes in the input capacitive loading. A replacement cell may have a shorter delay, but its driver may have a longer delay, offsetting any gains in the accumulated delay for the path. The process of finding the right cell is also computationally expensive, as all drive strength choices are typically tried out for every stage of the signal path. This makes the use of more drive strengths in a cell library impractical.
Various solutions have been proposed for the timing closure problem, which include better wire load prediction, integrated timing optimization and placement, “logical effort” and “gain” based timing optimization. The integrated placement and timing optimization compromises the quality of both timing and placement. “Logical effort” and “gain” based optimization over-constrain the placement stage to produce the right wire loads. These last two approaches attempt to avoid the computational cost of using discrete drive strengths by building continuous models of cells, mapping the delay capabilities of the cells versus their size, and using the resulting simplified models to solve the timing optimization problem. After solving the problem using these simplified models, cells based on continuous parameters are mapped to discrete components from the cell library. The wire load values are still required to be known. The quality of the modeling, mapping delay capabilities versus their size, and the number of the discrete choices in the library are critical issues with these approaches. In sum, these two approaches are often computationally complex and inaccurate.
Accordingly, there is a need for an improved design methodology where timing optimization and placement can be preformed independently in the most efficient manner and an initial timing optimization is performed independently of the wire loads.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides improved apparatus and methods for generating design netlists which meet timing and performance specifications of a circuit design. Preferably, power usage is kept low, and the design, placement and routing procedures of chip design flow are kept as independent as possible. These improved apparatus and methods rely on a special cell library having the property of constant replacement delays, as defined below, and preferably a relatively large, but still discrete choices of drive strengths. A set of logic cells is called a “family” if each member implements the same logic function, but the members of a particular family may have different electrical properties, like signal delays depending on the drive and load specifications. In one embodiment of a constant replacement delay cell library, members of each logic family share the same logic function, and the same set of replacement delays, which may be different for different signal paths. Each member of the family is designed to drive a specific load from a sorted set of uniformly increasing loads. Replacement delays of each member under this specific load is the same when the member cell is driven by a typical driver. A cell family thus has a load range, a set of fixed replacement delays for the particular load for each member, and a common set of timing constraints, such as setup and hold times, correspondin
Beyer Weaver & Thomas LLP.
Library Technologies, Inc.
Nelms David
Olynick, Esq. Mary R.
Pham Ly Duy
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