Apparatus and methods for testing memory devices

Details Apparatus and methods for testing memory devices Apparatus and methods for testing memory devices

2006-06-26

2008-09-02

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S200000, C365S201000

Reexamination Certificate

active

07421630

ABSTRACT:
Each match line of a memory device such as a content addressable memory (CAM) device and a related part of a priority encoder can be separately tested. In test mode, all match lines are first reset/disabled. A write enable pulse signal enables a match line corresponding to a CAM word line at a decoded address to be gated to the priority encoder of the CAM device. The CAM memory storage location and the comparand register are each loaded with the same test entry. A search is performed for the test entry. If the enabled match line is asserted and the priority encoder outputs the address corresponding to the CAM memory storage location, the test is successful. If not there is a match line error or a defect in the priority encoder.

REFERENCES:
patent: 5034923 (1991-07-01), Kuo et al.
patent: 5107501 (1992-04-01), Zorian
patent: 5400281 (1995-03-01), Morigami
patent: 6275426 (2001-08-01), Srinivasan et al.
patent: 7002823 (2006-02-01), Ichiriu

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