Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2005-10-04
2005-10-04
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S041000, C326S113000
Reexamination Certificate
active
06952114
ABSTRACT:
A programmable logic device (PLD) includes programmable electronic circuitry. The programmable electronic circuitry allows programming the functionality of the PLD. The programmable electronic circuitry includes one or more of programmable interconnects, pass devices, look-up table circuits, and/or multi-input logic circuits. Each of the programmable interconnects, pass devices, look-up table circuits, and/or multi-input logic circuits includes one or more of dynamic threshold metal oxide semiconductor (DTMOS) transistors, fully depleted metal oxide semiconductor (FDMOS) transistors, partially depleted metal oxide semiconductor (PDMOS) transistors, and/or double-gate metal oxide semiconductor transistors.
REFERENCES:
patent: 4952824 (1990-08-01), Kamuro
patent: 4972105 (1990-11-01), Burton et al.
patent: 5309046 (1994-05-01), Steele
patent: 6365465 (2002-04-01), Chan et al.
patent: 6369608 (2002-04-01), Lesea et al.
patent: 6445209 (2002-09-01), Young et al.
patent: 6515511 (2003-02-01), Sugibayashi et al.
patent: 6529040 (2003-03-01), Carberry et al.
patent: 1304803 (2003-04-01), None
patent: 2003179141 (2003-06-01), None
Toru Nakura et al., “A 3.6-Gb/s 340-mW 16:1 Pipe-Lined Multiplexer Using 0.18μm SOI-CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 35, No. 5, May 2000, pp. 751-756.
Fariborz Assaderaghi et al., “A Dynamic Threshold Voltage MOSFET (DTMOS) For Ultra-Low Voltage Operation,” IEEE, 1994, pp. 809-812, no month.
Brandon Chase, “Rushing The Double-Gate,” Scientific American: Technology and Business, Mar. 1999, 2 pgs.
Ricardo Gonzalez et al., “Supply and Threshold Voltage Scaling For Low Power CMOS,” IEEE Journal of Solid-State Circuits, vol. 32, No. 8, Aug. 1997, pp. 1210-1216.
“IBM Research News, IBM Advances New Form of Transistor To Improve Chips,” http://www.research.ibm.com/resources
ews/20011203_transisotr.shtml, Dec. 3, 2001, 2 pgs.
Altera Corporation
O'Keefe Egan & Peterman, LLP
Tan Vibol
LandOfFree
Apparatus and methods for silicon-on-insulator transistors... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and methods for silicon-on-insulator transistors..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and methods for silicon-on-insulator transistors... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3468423