Apparatus and methods for sharing cache among processors

Details Apparatus and methods for sharing cache among processors Apparatus and methods for sharing cache among processors

2005-08-16

2005-08-16

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S202000, C711S145000

Reexamination Certificate

active

06931489

ABSTRACT:
A processing system including a plurality of processors, a cache data array, and a crossbar interface connecting the processors with the cache data array. Each processor includes a tag array mapped to the cache data array. In another embodiment, the cache data array includes a plurality of sub-arrays accessible via a plurality of ports of the crossbar interface. The system allows an upper-level cache data array to be shared among processors while cache latency is reduced.

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