Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2003-10-03
2004-12-07
Le, Don (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S041000
Reexamination Certificate
active
06828822
ABSTRACT:
TECHNICAL FIELD
The inventive concepts relate generally to integrated circuit (IC) memory interfaces and, more particularly, to shared memory interfaces in programmable logic devices (PLDs).
BACKGROUND
Modem PLDs often interface with a variety of memory devices. Each type of memory typically uses a particular or specialized interface that complies with the specifications and protocols for that type of memory. Thus, to have the ability to interface with various types of memory, the PLD includes a number of input and output lines for each type of memory.
The specialized or dedicated input and output lines for the various types of memory increase the number of input/output pins for the PLD. Unfortunately, the increase in the number of pins results in larger packages and physical footprints for PLDs. Furthermore, the larger number of pins increases the cost of the PLDs and, hence, the systems within which they reside. A need therefore exists for providing memory interfaces in PLDs that overcome the disadvantages of conventional memory interfaces.
SUMMARY
This invention in contemplates configurable memory interfaces for PLDs. One aspect of the invention relates to apparatus for memory controllers for PLDs. In one illustrative embodiment, a PLD according to the invention includes a memory controller and an arbitration circuitry. The memory controller includes two controllers. One controller is configured to communicate via a shared interface with one memory external to the PLD. The other controller is configured to communicate via the shared interface with another memory external to the PLD. The arbitration circuitry arbitrates ownership of the shared memory interface by the two controllers.
In another illustrative embodiment, a data-processing system according to the invention includes a PLD. The PLD includes two memory controllers and a configurable memory interface. Each memory controller couples to a respective memory external to the PLD. The configurable memory interface is adapted to provide in a selectable manner a shared memory interface. The shared memory interface is configured to provide communication between the memory controllers and the respective external memories.
Another aspect of the invention concerns methods of processing information. In one illustrative embodiment, a method of processing information using a PLD includes communicating via a shared interface with a memory. The memory is external to the PLD. The method also includes communicating via the shared interface with another memory that is external to the PLD. The method further includes arbitrating ownership of the shared interface by the controllers.
REFERENCES:
patent: 6581145 (2003-06-01), Lu et al.
patent: 6605960 (2003-08-01), Veenstra et al.
Bellis Andrew J.
Dhanoa Kulwinder
Draper Andrew
Altera Corporation
Le Don
O'Keefe Egan & Peterman, LLP
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