Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2001-04-16
2002-07-23
Niebling, John F. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S121000
Reexamination Certificate
active
06423579
ABSTRACT:
TECHNICAL FIELD
The present invention relates to apparatus and methods for providing substrate structures having metallic layers for microelectronics devices such as, for example, chip-on-board packages, board-on-chip packages, dynamic random access memory packages, micro-ball grid array packages, and the like.
BACKGROUND OF THE INVENTION
As the trend toward decreasing the size and increasing the density of microelectronics packages continues, surface mounted chip-on-board (COB) packages, ball grid array (BGA) packages, and chip-scale-packages (CSP's) are commonly used to increase packaging density and reduce lead lengths for improving die performance. In such microelectronics packages, proper attachment of the die is a fundamental requirement.
FIG. 1
is a side cross-sectional view of a COB package
10
in accordance with the prior art. In this COB package, a die
12
has a bottom surface
14
attached to an electrically-insulative substrate layer
16
, such as a printed circuit board, by an attachment layer
26
. Typically the electrically-insulative substrate layer
16
is composed of bismaleimide triazine (BT), a polymer designed for printed circuit boards and the like, although other materials may be successfully used, including epoxy-based materials such as FR4 and FR5. The substrate layer
16
may have an internal network or mesh of interwoven fibers (not shown) to improve the strength and rigidity of the substrate layer
16
.
The COB package
10
has a plurality of bond pads
18
formed on the die
12
and a plurality of contact pads
20
formed on the substrate layer
16
. A lead wire
22
electrically couples each bond pad
18
to one of the contact pads
20
in the conventional manner. An encapsulating material
24
(or glob top) is formed over the die
12
, the bond pads
18
, the contact pads
20
, and the lead wires
22
to hermetically seal and protect these sensitive components from mechanical stress, humidity, oxidation, and other harmful elements.
Successful die attachment involves proper and consistent alignment of the die to a packaging substrate for improved automatic bonding yield. The die attachment should desirably be uniform and void-free over the contact area between the bottom surface
14
and the attachment surface
28
to provide good mechanical strength and thermal conduction. The die attachment should also be free of flakes or other debris which may later come loose and cause a malfunction of the microelectronics package.
Typically, the die
12
may be attached to the substrate layer
16
by applying an adhesive material, such as an epoxy adhesive, onto a die attachment surface
28
. The die
12
is then positioned over the epoxy adhesive and pressed against the epoxy adhesive to form a thin, uniform adhesive layer
26
between the bottom surface
14
of the die
12
and the die attachment surface. The adhesive layer
26
may then be cured, such as by heating the COB package
10
in an oven, to bond the die
12
to the substrate layer
16
.
Alternately, the die
12
may be eutectically bonded to the substrate layer
16
. Eutectic bonding takes place when two materials melt together (alloy) at a lower temperature than either of them separately. The two eutectic materials most commonly used for die attachment are gold and silicon. Although the melting point of gold is 1063° C. and the melting point of silicon is 1415° C., when the two materials are mixed together, they alloy at about 380° C. Methods of eutectic die attachment are described, for example, in U.S. Pat. No. 5,037,778 issued to Stark and Whitcomb, and in U.S. Pat. No. 5,760,473 issued to Dickson and Max, which patents are incorporated herein by reference.
For eutectic die attachment, a layer of gold may be plated onto the die attachment surface
28
. The COB package
10
may then be heated so that the gold layer alloys with the silicon bottom surface
14
of the die
12
to form the attachment layer
26
. Alternately, a layer of alloy material composed of gold and silicon may be place on the attachment surface
28
, and the COB package
10
heated so the gold and silicon layer alloys and bonds with the silicon bottom surface
14
and silicon attachment surface
28
. With the die
12
located in the desired position, the die is compressed against the liquid gold-silicon alloy and moved in a “scrubbing” action to form the eutectic attachment layer
26
. The COB package
10
is then cooled to complete the eutectic bond, thereby attaching the die
12
to the substrate layer
16
.
Die attachment using an epoxy adhesive layer is favored over eutectic bonding for its economy and ease of processing. Epoxy adhesives, however, do not provide the strength of eutectic bonding, and may decompose at high temperatures, such as those experienced during bonding of the bond pads
18
and contact pads
20
and sealing of the COB package
10
. Also, the attachment surface
28
of the substrate layer
16
may contain voids or surface irregularities that degrade die attachment, particularly those substrate layers having an interwoven mesh of fibers.
SUMMARY OF THE INVENTION
The present invention relates to apparatus and methods for providing substrate structures having metallic layers for microelectronics devices. In one aspect of the invention, an apparatus includes an electrically-insulative substrate layer, and a metallic layer attached to the electrically-insulative substrate layer, the metallic layer being attachable to a bottom surface of the microelectronics device. The metallic layer may advantageously provide a surface free from voids or irregularities for improved attachment of microelectronics devices. The metallic layer may also provide improved conduction of thermal energy away from the device, shielding from electromagnetic interference, a moisture barrier between the device and the substrate, and may serve as a convenient ground channel. In one aspect, the metallic layer may be continuous layer. Alternately, the metallic layer may be segmented into a plurality of closely-fitted pieces, or a plurality of spaced-apart pieces separated by expansion joints.
In another aspect, an apparatus may include a second metallic layer formed on the electrically-insulative substrate layer opposite from the first metallic layer. The second metallic layer may improve rigidity of the substrate layer and may provide additional shielding for the die from electromagnetic interference. Alternately, a solder resist layer may be formed on the first metallic layer to protect and mask the first metallic layer during processing. In a further aspect, a plating layer is formed on the second metallic layer.
In yet another aspect, a microelectronics package includes an electrically-insulative substrate layer, a metallic layer attached to the electrically-insulative substrate surface, an attachment layer formed on at least part of the metallic layer, and a die having a bottom surface attached to the attachment layer. The attachment layer may be an adhesive layer, or alternately, a eutectic layer. In another aspect, a microelectronics package may include a second metallic layer attached to the electrically-insulative substrate layer substantially opposite from the first metallic layer. In still another aspect, a plating lever may be disposed on the second metallic layer.
REFERENCES:
patent: 5586007 (1996-12-01), Funada
patent: 5821614 (1998-10-01), Hashimoto et al.
patent: 5866949 (1999-02-01), Schueller
patent: 6025640 (2000-02-01), Yagi et al.
patent: 6066515 (2000-05-01), Schoenfeld
Jiang Tongbi
Moden Walter L.
Niebling John F.
Zarreke David A.
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