Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2008-01-22
2008-01-22
Zarabian, Amir (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S230060, C326S040000, C326S039000
Reexamination Certificate
active
07321518
ABSTRACT:
An integrated circuit (IC) includes a redundancy feature. The redundancy feature is provided by a redundancy circuitry within the IC. The redundancy circuitry is configured to provide the redundancy by using a decoder circuitry. The decoder circuitry receives and decodes coded defect information from a set of circuit elements adapted to provide the coded defect information.
REFERENCES:
patent: 4281398 (1981-07-01), McKenny et al.
patent: 4724422 (1988-02-01), Golab
patent: 4747080 (1988-05-01), Yamada
patent: 4829481 (1989-05-01), Johnson et al.
patent: 4887239 (1989-12-01), Turner
patent: 5349555 (1994-09-01), Nakajima
patent: 5485102 (1996-01-01), Cliff et al.
patent: 5796662 (1998-08-01), Kalter et al.
patent: 5821770 (1998-10-01), Rees
patent: 5825698 (1998-10-01), Kim et al.
patent: 6020777 (2000-02-01), Bracchitta et al.
patent: 6115300 (2000-09-01), Massoumi et al.
patent: 6205050 (2001-03-01), Tamaki
patent: 6215173 (2001-04-01), Echigoya
patent: 6215715 (2001-04-01), Lee et al.
patent: 6219286 (2001-04-01), Fuchigami et al.
patent: 6236241 (2001-05-01), Liu et al.
patent: 6281739 (2001-08-01), Matsui
patent: 6366508 (2002-04-01), Agrawal et al.
patent: 6404264 (2002-06-01), Daniel et al.
patent: 6552938 (2003-04-01), Anand et al.
patent: 6600686 (2003-07-01), Huh et al.
patent: 6732229 (2004-05-01), Leung et al.
patent: 7047465 (2006-05-01), Trimberger
patent: 7061815 (2006-06-01), Ahmad
patent: 2002/0105854 (2002-08-01), Huh et al.
patent: 2003/0206477 (2003-11-01), Waller et al.
patent: 2004/0022110 (2004-02-01), Haraguchi et al.
patent: 2004/0027893 (2004-02-01), Kurita
Ouellette et al., “Shared Fuse Macro For Multiple Embedded Memory Devices With Redundancy”, IEEE Custom Integrated Circuits Conference, 2001, pp. 191-194.
McCollum et al., “Reliability Of Antifuse-Based Field Programmable Gate Arrays For Military And Aerospace Applications”, Actel Corporation, Abstract, Sep. 2001, 6 pgs.
Benedetto et al., “Amorphous Silicon Antifuse Programmable-Array-Logic Devices For High Reliability Space Applications”, UTMC Microelectronic Systems, Jan. 2002, 4 pgs.
Laville et al., “Integrated Offset Trimming Technique”, 27thEuropean Solid-State Circuits Conference, Sep. 2001, 4 pgs.
Actel, Reliability Considerations For Automotive FPGAs, White Paper, Sep. 2003, 17 pgs.
MRAM Redundancy Scheme (prior art available prior to filing date of the present application).
Chong Yan
Huang Joseph
Pan Philip
Sung Chiakang
Altera Corporation
Law Offices of Maximilian R. Peterson
Weinberg Michael
Zarabian Amir
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