Apparatus and methods for predicting multiple product chip...

Details Apparatus and methods for predicting multiple product chip... Apparatus and methods for predicting multiple product chip...

2001-11-14

2004-05-04

Picard, Leo (Department: 2125)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C702S183000

Reexamination Certificate

active

06732002

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to methods and apparatus for detecting defects in a semiconductor test structure to thereby predict product yield. More particularly, it relates to voltage contrast techniques for inspecting test structures to predict product yield across multiple product chips having different critical areas.
A voltage contrast inspection of a test structure is accomplished with a scanning electron microscope. The voltage contrast technique operates on the basis that potential differences in the various locations of a sample under examination cause differences in secondary electron emission intensities when the sample is the target of an electron beam. The potential state of the scanned area is acquired as a voltage contrast image such that a low potential portion of, for example, a wiring pattern might be displayed as bright (intensity of the secondary electron emission is high) and a high potential portion might be displayed as dark (lower intensity secondary electron emission). Alternatively, the system may be configured such that a low potential portion might be displayed as dark and a high potential portion might be displayed as bright.
A secondary electron detector is used to measure the intensity of the secondary electron emission that originates from the path swept by the scanning electron beam. Images may then be generated from these electron emissions. A defective portion can be identified from the potential state or appearance of the portion under inspection. The portion under inspection is typically designed to produce a particular potential and resulting brightness level in an image during the voltage contrast test. Hence, when the scanned portion's potential and resulting image appearance differs significantly from the expected result, the scanned portion is classified a defect.
One inventive test structure designed by the present assignee is disclosed in co-pending U.S. patent application Ser. No. 09/648,093 by Akella V.S. Satya et al., filed Aug. 25, 2000, which application is incorporated herein in its entirety. This test structure is designed to have alternating high and low potential conductive lines during a voltage contrast inspection. In one inspection application, the low potential lines are at ground potential, while the high potential lines are at a floating potential. However, if a line that is meant to remain floating shorts to an adjacent grounded line, both lines will now produce a low potential during a voltage contrast inspection. If there is an open defect present within a line that is supposedly coupled to ground, this open will cause a portion of the line to be left at a floating potential to thereby produce a high potential during the voltage contrast inspection. Both open and short defects causes two adjacent lines to have a same potential during the voltage inspection.
The results from inspecting a test structure may then be used to predict yield of a product chip that is fabricated with the same process as the test structure. Given a particular defect, yield prediction of a chip (i.e., the probability that the chip will fail) depends on the critical area associated with the particular defect and the probability that the particular defect will fall within the associated critical area. Critical area refers to the total area of the chip as a function of the defect size in which the defect can occur and cause a fault (e.g., a short or open).
FIGS. 1A and 1B
illustrate the concept of critical area. Each specific configuration of semiconductor circuit, pattern, and test structure has an associated critical area for a given defect size. Additionally, each specific circuit, pattern, and test structure has an associated critical area curve as a function of defect size.
FIG. 1A
is a diagrammatic top view of a simple test structure
100
having two conductive lines
102
a
and
102
b
. The lines
102
a
and
102
b
both have a width
104
and a line spacing
106
.
FIG. 1B
is a graph of critical area as a function of defect size for the test structure
100
of
FIG. 1A. A
defect
110
that is sized to be less than the line spacing will not cause a fault (e.g., short) in any area of test structure
100
. As shown in
FIG. 1B
, critical area is zero for defects sizes less than width
106
. However, a defect
108
having a size (e.g., radius) equal to or greater than the width size
106
will have an associated critical area in which it causes a fault. For example, if the defect
108
is positioned in a narrow area
109
that runs down the centerline between the two lines
102
, it will cause a fault by shorting the two lines
102
. This narrow area
109
is the critical area for defect
108
. The critical area will continue to increase for increasingly sized defects until a critical area plateaus is reached. This plateau is reached at a particular defect size for which the critical area equals the area of the test structure. For this test structure
100
, the critical area plateaus at a defect size that is twice the width of the line spacing
106
.
Although the yield for a product chip having the same critical area may be predicted based on the test structure, the yield for a product chip having a different critical area than the test structure may not be accurately calculated using the test structure defect data.
FIG. 2
shows illustrative plots of critical area for a test structure as a function of defect size, critical area of a particular product chip as a function of defect size, and the number of defects measured for the test structure as a function of defect size.
The defect counts are measured on the test structure, for example, for defect sizes greater than
204
. In this example, defects having a size less than
204
are simply not captured because of limitation in the metrology tool. Thus, the defect size distribution (i.e., defect count as a function of defect size) for the test structure may be plotted for defect sizes
204
and higher.
Yield for a particular chip is based on the area under both of its related defect size distribution and critical area curves. Thus, yield for a product chip that has a different critical area than the test structure's critical area is typically based on the product's critical area curve (i.e., not the test structure's critical area curve) and defect size distribution curve. As shown, yield for the product chip is equal to area
206
. Although the critical area of the product chip is known, its defect size distribution curve is not known within tolerable certainty. In the illustrated example, defect size distribution has an associated margin of error
208
. Unfortunately, this uncertainty is introduced into the yield calculation for the product. As a result, a product yield prediction that is based on a measured defect size distribution curve may be inaccurate and unreliable due to the inaccuracy of the defect size distribution curve.
Accordingly, there is a need for mechanisms for more accurately predicting yield across multiple product chips having different critical areas.
SUMMARY OF THE INVENTION
Accordingly, a test chip having a plurality of test structures is provided that is designed so that defect sampling may be customized to obtain different critical areas from the test chip. Each test structure is conceptually divided into a plurality of unit cells (e.g., a pair of grounded and floating conductive lines). The defects of a percentage of unit cells may then be sampled for each test structure to conceptually form a sub test structure that has a different size than the original test structure. The percentage of unit cells that are sampled for each test structure is chosen so as to achieve a specific critical area curve. The defects from each sampled set of unit cells may then combined to determine yield for a product chip having the same specific critical area curve.
These defect sampling techniques are customizable for different product chips having different critical areas to thereby predict product yield for such product chips using the

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