Apparatus and methods for multi-level sensing in a memory array

Details Apparatus and methods for multi-level sensing in a memory array Apparatus and methods for multi-level sensing in a memory array

2006-11-28

2006-11-28

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S194000

Reexamination Certificate

active

07142464

ABSTRACT:
A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.

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