Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-13
2003-06-17
Phan, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06581193
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to reticle and integrated circuit design and fabrication systems. More specifically, the invention relates to mechanisms for generating and inspecting reticles and integrated circuits.
Generation of reticles and subsequent optical inspection of such reticles have become standard steps in the production of semiconductors. Initially, circuit designers provide circuit pattern data, which describes a particular integrated circuit (IC) design, to a reticle production system, or reticle writer. The circuit pattern data is typically in the form of a representational layout of the physical layers of the fabricated IC device. The representational layout typically includes a representational layer for each physical layer of the IC device (e.g., gate oxide, polysilicon, metallization, etc.), wherein each representational layer is composed of a plurality of polygons that define a layer's patterning of the particular IC device.
The reticle writer uses the circuit pattern data to write (e.g., typically, an electron beam writer or laser scanner is used to expose a reticle pattern) a plurality of reticles that will later be used to fabricate the particular IC design. A reticle inspection system may then inspect the reticle for defects that may have occurred during the production of the reticles.
A reticle or photomask is an optical element containing transparent and opaque, semi-transparent, and phase shifting regions which together define the pattern of coplanar features in an electronic device such as an integrated circuit. Reticles are used during photolithography to define specified regions of a semiconductor wafer for etching, ion implantation, or other fabrication processes. For many modern integrated circuit designs, an optical reticle's features are between about 1 and about 5 times larger than the corresponding features on the wafer. For other exposure systems (e.g., x-ray, e-beam, and extreme ultraviolet) a similar range of reduction ratios also apply.
Optical reticles are typically made from a transparent medium such as a borosilicate glass or quartz plate on which is deposited on an opaque and/or semi-opaque layer of chromium or other suitable material. However, other mask technologies are employed for direct e-beam exposure (e.g., stencil masks), x-ray exposure (e.g., absorber masks), etc. The reticle pattern may be created by a laser or an e-beam direct write technique, for example, both of which are widely used in the art.
After fabrication of each reticle or group of reticles, each reticle is typically inspected by illuminating it with light emanating from a controlled illuminator. An optical image of the reticle is constructed based on the portion of the light reflected, transmitted, or otherwise directed to a light sensor. Another way to inspect a reticle is accomplished by directing a beam of electrons from a scanning electron microscope towards the reticle. An image of the reticle is constructed based on secondary and backscattered electrons emitted from the reticle in response to the beam of electron towards a detector. Such inspection techniques and apparatus are well known in the art and are embodied in various commercial products such as many of those available from KLA-Tencor Corporation of San Jose, Calif.
During a conventional inspection process, a target image of a test structure on the reticle is typically compared to a reference image. The reference image is either generated from the circuit pattern data or from an adjacent die on the reticle itself. Either way, the target image features are analyzed and compared with corresponding features of the reference image. Each feature difference is then compared against a threshold value. If the target image feature varies from the reference feature by more than the predetermined threshold, a defect is defined. Similar techniques may be utilized to inspect an integrated circuit (IC).
Prior to comparing a target image to its corresponding reference image, the target image which corresponds to the reference image must be accurately located. Conventionally, the corresponding target image is located manually by first locating a unique target image that is adjacent to the target image of the test structure to be tested. The unique image is typically located by searching for an imaged target pattern from the sample that most closely matches a unique reference pattern selected from the original design data. The location of the reference pattern can then be used to form a frame of reference for the subsequent inspection or metrology.
Although conventional reticle and IC inspections provide adequate searching mechanisms under some conditions, the searching mechanisms fail when the unique target images significantly differ from their corresponding unique reference images. Several different effects may contribute to the target images differing from the reference images. When the target structures are fabricated from original design patterns which are also used as the reference images, the fabrication process itself introduces discrepancies between the target structures and the reference images. By way of examples, the target structures may become tapered and reduced in size. Target structure corners may also become rounded and/or warped, while edges may become roughened. Imaging of target structures also introduces discrepancies between the reference and target images. The imaging process may result in edge enhancement, scan persistence, and contrast changes between the substrate and material, as compared with the design patterns (reference images). Edges may also appear thickened and charge shadowing may occur. These differences between the target and reference images often make it very difficult to locate a target image which corresponds to a particular reference image.
Accordingly, there is a need for improved mechanisms for providing reference images for locating corresponding target images. Additionally, there is a need for reduction in the discrepancies between the reference and corresponding target images caused by process and/or imaging effects resulting from fabricating and imaging of the corresponding test structures.
SUMMARY OF THE INVENTION
Accordingly, mechanisms are provided for generating reference images (or modifying existing reference images) so that the reference images at least partially simulate one or more process effects. In one specific implementation, the reference images simulate feature tapering, corner rounding, and feature shrinkage, which effects are typically introduced during fabrications of the corresponding target structures. Additional mechanisms are provided for generating or modifying reference images so that they at least partially simulate imaging effects. In a specific embodiment, simulated imaging effects include edge enhancement, substrate and material contrast, and scan persistence.
The reference images may then be utilized to locate target images of patterns on a sample, such as a reticle or integrated circuit. In one embodiment, a recipe is formed based on the simulated reference images. The recipe is configured to be used by a metrology tool to automatically locate corresponding target structures on a sample. In this application, the recipe includes information associated with each reference image that specifies the kind of test to be performed on a test structure that is located proximate to the target structures. For example, the information includes an offset distance from such target structure to such test structure and the type of test structure to be measured. In one implementation, the information specifies whether the structure to be measured is a line, trench, hole, or post. The information preferably also specifies whether to measure from outer most edge to outer most edge of such structure or inner most edge to inner most edge.
In a specific embodiment, a method of generating a test recipe for a metrology tool is disclosed. A plurality of first reference images that are designed to be used to fabri
Ananthanarayanan Mohan
McGhee Ridge C.
Watts Robert A.
Beyer Weaver & Thomas LLP.
KLA-Tencor
Olynick, Esq. Mary R.
Phan Trong
LandOfFree
Apparatus and methods for modeling process effects and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and methods for modeling process effects and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and methods for modeling process effects and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3143915