Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-08-24
2003-05-06
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06560755
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to apparatus and methods for modeling and simulating the effect of mismatch. In particular, this invention relates to apparatus and methods for modeling and simulating the effect of mismatch in design flows of integrated circuits.
BACKGROUND OF THE INVENTION
Circuit designers typically use design tools to design integrated circuits. The most common design tools are the so-called simulated-program-with-integrated-circuit-emphasis (SPICE) and the fast device level simulators (e.g., Star-Sim, ATS, MACH TA, and TIMEMILL). Typically, design tools, such as SPICE and fast device level simulators, describe individual device and its connections in a line-by-line manner. Examples of individual devices are resistor, capacitor, inductor, bipolar junction transistor, and metal oxide semiconductor field effect transistor (MOSFET). In a design tool, each line, which includes a description of a device, is sometimes referred to as a device specification instance.
FIG. 1A
illustrates an exemplary netlist developed by a design tool, such as SPICE. As shown in
FIG. 1A
, a netlist
101
typically includes three sections: a circuit description section
103
, a models section
105
, and an analysis section
107
. The circuit description section
103
contains a description of each device and sub-circuit as well as interconnections between the devices and sub-circuits within an integrated circuit. The models section
105
contains a description of individual device and sub-circuit behavior. Typically, the models section
105
comprises a library of model parameters, model parameter values, and model equations. Generally, the behavior of each type of device (e.g., a MOSFET) can be simulated by at least one model equation, which includes a combination of model parameters. The analysis section
107
typically includes analysis instructions to simulate a device, sub-circuit, or circuit (e.g., output voltage over time) using information in the circuit description section
103
and the models section
105
. In existing design tools, such as SPICE, simulations performed typically do not account for the effect of the mismatch phenomenon.
The mismatch phenomenon (“mismatch”) can be defined as the difference in device performance for similarly/identically designed devices operating under the same bias conditions. The effect of mismatch is not limited to only among devices; mismatch in device characteristics can lead to performance differences among similarly/identically designed circuits operating under the same bias conditions. Generally, whether among devices or circuits, the performance difference caused by mismatch is not a constant but has a statistical distribution. In particular, the effect of mismatch is dependent on device geometry, distances between devices, layout style, and temperature applied to a device.
Mismatch is a limiting factor in both analog and digital circuitry. As the demand for more complex integrated circuits continues to drive the industry to reduce device geometry, the effect of mismatch becomes increasingly intolerable. Thus, although mismatch has long been recognized and characterized, the effect of mismatch has in recent years become a more important problem in integrated circuit design.
In order to safeguard against design specification failures caused by mismatch, some designers have adopted overly conservative design and simulation strategies. For example, devices are intentionally designed to have a larger geometry or placed in a particular layout style to minimize the effect of mismatch. Major drawbacks of this strategy include circuit performance degradation and an increase in cost due to an increase in chip area. In another strategy, global variation statistics are used to simulate the effect of mismatch, which is predominately a local effect. For example, a designer assigns parameter distributions to selected model parameters and performs Monte Carlo simulations based on those parameter distributions. Results obtained from such simulations typically over-estimate the effect of mismatch because a global variation generally does not account for mismatch dependence on device geometry, distances between devices, layout styles, and other factors.
Thus, it is desirable to provide apparatus and methods to more accurately and efficiently simulate the effect of device mismatch in integrated circuit design flows.
SUMMARY OF THE INVENTION
This invention provides apparatus and methods for modeling and simulating the effect of device mismatch in integrated circuit design flows. In particular, this invention is capable of modeling the effect of mismatch in individual devices or sub-circuits. Further, using such modeling information, the effect of mismatch can be simulated in design flows of integrated circuits.
An exemplary method for simulating the effect of mismatch in design flows comprises: receiving measured data, receiving an original model, extracting a mismatch model based on the measured data and the original model, attaching the mismatch model to a netlist to obtain a modified netlist, and simulating an effect of mismatch based on the modified netlist. In one embodiment, the extracting of a mismatch model includes selecting a set of model parameters, generating a distribution of mismatch values for each of the model parameters, extracting a set of linking coefficients based on the mismatch values, and extracting a mismatch model based on the set of linking coefficients. In another embodiment, the attaching of the mismatch model to the netlist includes determining a number of layers in the netlist, generating a copy of a lower layer in the netlist, where the copy of the lower layer includes a reference to a mismatch model definition, generating a copy of a higher layer in the netlist, replacing a reference to the lower layer in the higher layer by a reference to the copy of the lower layer, and generating a new model definition. In an exemplary embodiment, the lower layer includes a device specification instance and the higher layer includes a sub-circuit specification instance. In an exemplary embodiment, a layer can be referred to as a sub-circuit layer if it contains a reference to a sub-circuit.
An exemplary method for extracting mismatch values that are used to simulate the effect of mismatch in design flows comprises: receiving measured data, receiving an original model, selecting a set of model parameters, generating a distribution of mismatch values for each of the model parameters based on the measure data and the original model, extracting a set of linking coefficients based on the mismatch values, and extracting the mismatch model based on the set of linking coefficients. In one embodiment, selecting a set of model parameters includes adding a value to a model parameter, performing a device performance simulation based on the model parameter, repeating the adding and performing for all model parameters, ranking the model parameters based on the device performance simulation, and selecting a set of model parameters based on the ranking. In another embodiment, instead of performing device simulations, sub-circuit simulations are performed.
In another embodiment, generating a distribution of mismatch values includes generating a number of target values, performing a set of simulations for each of the model parameters based on the target values, and generating a distribution of mismatch values for each of the model parameters based on the simulations. In an exemplary embodiment, the method further comprises generating correlation distributions among the set of model parameters based on the mismatch values.
Another exemplary method for simulating the effect of mismatch in design flows based on a mismatch model file, including a set of linking coefficients, and netlist information from a netlist comprises: extracting a set of modified model parameters based on the mismatch model file and the netlist information, attaching the set of modified model parameters to the netlist to obtain a modified netlist, simulating the netlis
Chen James Chieh-Tsung
Fang Jingkun
Liu Zhihong
Pang Xucheng
Xie Jushan
Cadence Design Systems Inc.
Pennie & Edmonds LLP
Siek Vuthe
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