Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-05-05
2001-12-25
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S041000, C326S038000
Reexamination Certificate
active
06333641
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to programmable digital logic. More particularly, this invention relates to a technique for dynamically defining variably sized autonomous sub-arrays within a programmable gate array.
BACKGROUND OF THE INVENTION
Existing programmable logic devices do not provide a mechanism to maintain the autonomy of programmed functions especially when the functions are independently designed. Moreover, existing programmable logic devices do not provide dedicated bus routing resources for such programmed functions. Routing resources used for busing in existing programmable logic devices are typically uni-dimensional; namely, the routing resources are capable of conveying signals along one axis, but not along both axes.
FIG. 1
illustrates exemplary prior art routing architectures in programmable logic devices. A programmable logic device
100
implemented a s a standard field programmable gate array (FPGA) includes vertical routing lines
101
and horizontal routing lines
104
interconnected to logic modules
102
via local routing lines or interconnect
103
.
Current FPGA hierarchical routing relies upon segment lengths from short local routes (e.g., interconnect
103
) to chip-wide long routes (e.g., vertical routing lines
101
and horizontal routing lines
104
) to interconnect the various modules
102
. This routing hierarchy does not allow functions of variable size to be autonomously implemented in modules
102
.
Some FPGAs are equipped with chip-wide 3-state route resources which are commonly used for bussing. However, these 3-state resources are limited to bussing in one direction, either horizontally or vertically, but not both. Even in devices that contain 3-state resources in both dimensions (horizontally and vertically), such 3-state resources still do not interconnect. Moreover, these routing resources are not dedicated for busing.
Because of the undedicated nature of the conventional interconnect
101
and
104
, functions implemented across several modules
102
will incur performance degradation. Furthermore, autonomous functions that have logic commingled within a module
102
will incur additional performance degradation. Performance degradation due to the commingling of disparate logic is a significant obstacle in merging autonomous functions.
In view of the foregoing, it would be highly desirable to provide a mechanism for grouping bussed resources that is capable of simultaneously interconnecting logic modules in both a conventional local/global approach and in a bussed manner between local modules. Such a technique would allow function autonomy after merging.
SUMMARY OF THE INVENTION
The apparatus of the invention includes a programmable logic device comprising an array of logic modules, a standard interconnection grid, with vertical routing lines, horizontal routing lines, and local routing lines, and an omniversal bus functionally positioned over the array of logic modules. The array of logic modules includes selective links to the omniversal bus, such that the omniversal bus dynamically establishes autonomous sub-arrays of logic modules of variable sizes functionally attached to the omniversal bus. The omniversal bus of this invention is capable of transporting signals bi-directionally along both axes.
The non-segmented, programmable “omniversal” bus of the invention facilitates subdividing the module array into locally autonomous programmable sub-arrays. Each sub-array can be independently designed, optimized, mapped, placed, and routed. Individual sub-arrays may be of varying sizes and may be merged incrementally. For example, large designs (>250K gates) and very large designs (>1M gates) can be subdivided into manageable functions for autonomous implementation. During subsequent merging, autonomous function performance characteristics are maintained. Thus, independent third-party functions and other disparate functions can be seamlessly merged.
The omniversal bus is functionally connected to the logic modules via docking ports. In an exemplary embodiment, a docking port includes two kinds of resources: (1) point-to-point interconnect; and (2) collective interconnect. Point-to-point interconnect (“point interconnect”) allows a one-to-one correspondence of nodes among docking ports. Collective interconnect allows a one-to-n correspondence among docking ports. Point interconnect comprises a plurality of nodes. A point interconnect node can be connected to multiple collective interconnects for receiving various control signals. Point interconnect provides general address and data conveyance, whereas collective interconnect provides control.
REFERENCES:
patent: 4935734 (1990-06-01), Austin
patent: 5329470 (1994-07-01), Sample et al.
patent: 5455525 (1995-10-01), Ho et al.
patent: 5541530 (1996-07-01), Cliff et al.
patent: 5703498 (1997-12-01), Gould et al.
patent: 5796623 (1998-08-01), Butts et al.
patent: 5894228 (1999-04-01), Reddy et al.
patent: 5903165 (1999-05-01), Jones et al.
patent: 5943242 (1999-08-01), Vorbach et al.
patent: 5946219 (1999-08-01), Mason et al.
patent: 5963049 (1999-10-01), Cliff et al.
patent: 5999016 (1999-12-01), McClintock et al.
patent: 6021490 (2000-02-01), Vorbach et al.
patent: 6075380 (2000-06-01), Lane
patent: WO98/21725A2 (1998-05-01), None
patent: WO99/56394A1 (1999-11-01), None
Le Don Phu
Morphics Technology Inc.
Pennie & Edmonds LLP
Tokar Michael
LandOfFree
Apparatus and methods for dynamically defining variably... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and methods for dynamically defining variably..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and methods for dynamically defining variably... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2591920