Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Patent
1996-12-23
1999-08-10
Hoff, Marc S.
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
341118, H03M 110
Patent
active
059365617
ABSTRACT:
A digitally compensated multi-bit sigma-delta analog-to-digital converter may be used to achieve high resolution in analog-to-digital conversions using a low oversampling ratio and simplified hardware construction. The digitally compensated multi-bit sigma-delta analog-to-digital converter has a recycling converter which converts an analog signal to a digital signal and which recycles the converted signal at least one time through a sample hold circuit, an analog-to-digital converter and a digital-to-analog converter in order to obtain a 4 bit digital signal. A digital corrector converts the 4 bit digital signal to a 16 bit corrected digital signal. The 16 bit corrected digital signal is used to generate a digitally compensated digital signal and to generate a digital error code. The digitally compensated digital signal is obtained by adding the 16 bit corrected digital signal with a 16 bit calibrated digital signal using an adder. The nine least significant bits of the compensated digital signal, representing a calibration value indicative of the error in the converted digital signal, are obtained using a roundoff circuit and stored in memory. As a result, high resolution in analog-to-digital conversion can be obtained while achieving a low oversampling ratio and simplified hardware construction.
REFERENCES:
patent: 4612533 (1986-09-01), Evans
patent: 4903023 (1990-02-01), Evans et al.
patent: 4908621 (1990-03-01), Polonio et al.
patent: 5017920 (1991-05-01), French
patent: 5047772 (1991-09-01), Ribner
patent: 5381148 (1995-01-01), Mueck et al.
patent: 5635937 (1997-06-01), Lim et al.
Sarhang-Nejad et al., "A High-Resolution Multibit .EPSILON..increment. ADC with Digital Correction and Relaxed Amplifier Requirements", IEEE Journal of Solid-State Circuits, vol. 28, No 6, Jun. 1993, pp. 648-660.
Cataltepe et al., "Digitally Corrected Multi-Bit .EPSILON..increment. Data Converters", IEEE Proc. ISCAS '89, May 1989, pp. 647-650.
Larson et al., "Multibit Oversampled .EPSILON..increment.A/D Convertor With Digital Error Correction", Electron, Lett., vol. 24, Aug. 1988, pp. 1051-1052.
Walden et al., "Architectures for High-Order Multibit .EPSILON..increment. Modulators", IEEE Proc. ISCAS '90, pp. 895-898.
Hoff Marc S.
Jean Pierre Peguy
Samsung Electronics Co,. Ltd.
LandOfFree
Apparatus and methods for digitally compensated multi-bit sigma- does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and methods for digitally compensated multi-bit sigma-, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and methods for digitally compensated multi-bit sigma- will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1124349