Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2006-04-14
2009-06-16
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C365S207000, C365S189070
Reexamination Certificate
active
07548473
ABSTRACT:
A test circuit used for determining a fault in a memory device. The test circuit includes a read circuit configured to read memory cell contents in a memory device at a first time instant and second time instant. The test circuit includes a comparator that compares the contents at the first and second time instants. If the contents are different from one another, the comparator indicates that a fault has occurred. Test methods are also used to determine if a fault has occurred in a memory cell.
REFERENCES:
patent: 5179536 (1993-01-01), Kasa et al.
patent: 5311473 (1994-05-01), McClure et al.
patent: 5519712 (1996-05-01), Shu et al.
patent: 5539694 (1996-07-01), Rouy
patent: 5666324 (1997-09-01), Kosugi et al.
patent: 6122710 (2000-09-01), Kumar et al.
patent: 6418067 (2002-07-01), Watanabe et al.
patent: 6757209 (2004-06-01), Mak et al.
patent: 7130236 (2006-10-01), Rajwani et al.
patent: 7263010 (2007-08-01), Iwai et al.
patent: 7266036 (2007-09-01), Hayashi et al.
patent: 7277307 (2007-10-01), Yelluru
patent: 7382637 (2008-06-01), Rathnavelu et al.
patent: 7385863 (2008-06-01), Nishihara et al.
patent: 2002/0141259 (2002-10-01), Mak et al.
patent: 2003/0081449 (2003-05-01), Beucler
patent: 2004/0022115 (2004-02-01), Park et al.
Chen, Q. et al., “Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS,” Proceedings of the 23rd IEEE VLSI Test Symposium, May 2005, pp. 292-297.
Chen, Q. et al., “Efficient Testing of SRAM with optimized march sequences and novel DFT technique for emerging failures due to process variations,” IEEE Transactions on VLSI Systems, Nov. 2005, vol. 13, No. 11, pp. 1286-1295.
Anne Meixner, et al., Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique, Proceedings of the IEEE International Test Conference on Test and Design Validity, 1996, pp. 309-318, IEEE, Washington, DC, USA.
Bhunia Swarup
Chen Qikai
Mahmoodi Hamid
Roy Kaushik
Barnes and Thornburg LLP
Nguyen Tuan T.
Purdue Research Foundation
LandOfFree
Apparatus and methods for determining memory device faults does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and methods for determining memory device faults, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and methods for determining memory device faults will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4142417