Apparatus and methods for controlling pad conditioning head...

Abrading – Abrading process – With tool treating or forming

Reexamination Certificate

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C451S041000, C451S060000, C451S287000, C451S288000, C451S289000, C451S443000

Reexamination Certificate

active

06443815

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to chemical mechanical polishing (CMP) systems and techniques for improving the performance and effectiveness of CMP operations. Specifically, the present invention relates to carrier heads for wafers and pad conditioning pucks, in which repeatability is provided in measuring forces applied to the heads eccentrically of a main axis of the head are resisted, wherein the heads, with the wafers and the pucks, do not tilt in response to the eccentric forces, but instead the heads are allowed to move parallel to a wafer axis; and relates to facilities for CMP operations, such as facilities for supplying fluids to, and removing fluids from, the carrier heads for the CMP operations without interfering with the CMP operations.
DESCRIPTION OF THE RELATED ART
In the fabrication of semiconductor devices, there is a need to perform CMP operations, including polishing, buffing and wafer cleaning. For example, a typical semiconductor wafer may be made from silicon and may be a disk that is 200 mm or 300 mm in diameter. For ease of description, the term “wafer” is used below to describe and include such semiconductor wafers and other planar structures, or substrates, that are used to support electrical or electronic circuits.
Typically, integrated circuit devices are in the form of multi-level structures fabricated on such wafers. At the wafer level, transistor devices having diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired functional device. Patterned conductive layers are insulated from other conductive layers by dielectric materials. As more metallization levels and associated dielectric layers are formed, the need to planarize the dielectric material increases. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then metal CMP operations are performed to remove excess metallization.
In the prior art, CMP systems typically implement belt, orbital, or brush stations in which belts, pads, or brushes are used to scrub, buff, and polish one or both sides of a wafer. According to the type of CMP operation being performed, certain materials, such as slurry, are used to facilitate and enhance the CMP operation. For example, the slurry is most usually introduced onto a moving preparation surface, e.g., belt, pad, brush, and the like, and distributed over the preparation surface as well as the surface of the semiconductor wafer being buffed, polished, or otherwise prepared by the CMP process. The distribution is generally accomplished by a combination of the movement of the preparation surface, the movement of the semiconductor wafer and the friction created between the semiconductor wafer and the preparation surface.
In a typical CMP system, a wafer is mounted on a carrier with a surface of the wafer exposed. The carrier and the wafer rotate in a direction of rotation. The CMP process may be achieved, for example, when the exposed surface of the rotating wafer and a polishing pad are urged toward each other by a force, and when the exposed surface and the polishing pad move or rotate in a polishing pad direction. Some CMP processes require that a significant force be used at the time the rotating wafer is being polished by the polishing pad.
Normally, the polishing pads used in the CMP systems are composed of porous or fibrous materials. However, in some CMP systems, the polishing pads may contain fixed abrasive particles throughout their surfaces. Depending on the form of the polishing pad used, the slurry may be composed of an aqueous solution such as NH
4
OH, or DI water containing dispersed abrasive particles may be applied to the polishing pad, thereby creating an abrasive chemical solution between the polishing pad and the exposed surface of the wafer.
Several problems may be encountered while using a typical CMP system. One recurring problem is called “edge-effect,” which is caused when the CMP system polishes an edge of the wafer at a different rate than other regions of the wafer. The edge-effect is characterized by a non-uniform profile on the exposed surface of the wafer. The problems associated with edge-effect can be divided to two distinct categories. The first category relates to the so-called “pad rebound effect” resulting from the initial contact of the polishing pad with the edge of the wafer. When the polishing pad initially contacts the edge of the wafer, the pad rebounds (or bounces off) the edge, such that the pad may assume a wave-like shape. The wave-like shape may produce non-uniform profiles on the exposed surface of the wafer.
The second category is the “burn-off” effect. The burn-off effect occurs when a sharper edge of the wafer is excessively polished as it makes contact with the surface of the polishing pad. This happens because a considerable amount of pressure is exerted on the edge of the wafer as a result of the surface of the pad applying the force on a very small contact area of the exposed surface of the wafer (defined as the edge contact zone. As a consequence of the burn-off effect, the edges of the resulting polished wafers exhibit a burn ring that renders the edge region unusable for fabricating silicon devices.
Another shortcoming of conventional CMP systems is an inability to polish the surface of the wafer along a desired finishing layer profile. Ordinarily, the exposed surface of a wafer that has undergone some fabrication tends to be of a different thickness in the center region and varies in thickness out to the edge. In a typical conventional CMP system, the pad surface covers the entire exposed surface of the wafer. Such pad surface is designed to apply a force on a so-called “finishing layer” portion of the exposed surface of the wafer. As a result, all the regions of the finishing layer are polished until the finishing layer is substantially flat. Thus, the surface of the pad polishes the finishing layer irrespective of the wavy profile of the finishing layer, thereby causing the thickness of the finishing layer to be non-uniform. Some circuit fabrication applications require that a certain thickness of material be maintained in order to build a working device. For instance, if the finishing layer were a dielectric layer, a certain thickness would be needed in order to define metal lines and conductive vias therein.
These problems of prior CMP operations, and an unsolved need in the CMP art for a CMP system that enables precision and controlled polishing of specifically targeted wafer surface regions, while substantially eliminating damaging edge-effects, pad rebound effects, and edge burn-off effects, are discussed in related U.S. Pat. application Ser. No. 09/644,135 filed Aug. 22, 2000 for Subaperture Chemical Mechanical Polishing System and assigned to the assignee of the present application (the “related application”). The specification, claims and drawings of such related application are by this reference incorporated in the present application.
In such related application, a CMP system follows the topography of layer surfaces of the exposed surface of the wafer so as to create a CMP-processed layer surface which has a uniform thickness throughout. Such CMP system implements a rotating carrier in a subaperture polishing configuration, eliminating the above-mentioned drawbacks, edge-effects, pad rebound effects, and edge bum-off effects. For example, one embodiment of such CMP system includes a carrier having a top surface and a bottom region. The top surface of the carrier is designed to hold and rotate a wafer having one or more formed layers to be prepared. Further included is a preparation head, such as a polishing head, designed to be applied to at least a portion of the wafer, wherein the portion is less than an entire portion of the surface of the

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