Apparatus and methods for cell models for timing and power...

Details Apparatus and methods for cell models for timing and power... Apparatus and methods for cell models for timing and power...

2007-03-20

2007-03-20

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C703S014000

Reexamination Certificate

active

10839787

ABSTRACT:
A system for analyzing a circuit includes a computer. The computer operates on a model of the circuit. The model has an input, an output, and multiple controlled sources. The computer is configured to supply a stimulus to the input of the model of the circuit. The input stimulus has an associated value. Each of the multiple controlled sources has a current value derived from the input value. The computer is also configured to supply a stimulus to the output of the model. The output stimulus has an associated value. The computer is further configured to sweep the values for the input and output stimuli through a two sets of swept values, and to obtain an output current of the model of the circuit as a function of the swept values.

REFERENCES:
patent: 5047971 (1991-09-01), Horwitz
patent: 5373457 (1994-12-01), George et al.
patent: 5535370 (1996-07-01), Raman et al.
patent: 5857164 (1999-01-01), Wakita
patent: 6102960 (2000-08-01), Berman et al.
patent: 6615394 (2003-09-01), Ogawa et al.
patent: 6721922 (2004-04-01), Walters et al.
patent: 6789237 (2004-09-01), Ismail
patent: 6794674 (2004-09-01), Kusumoto
patent: 2001/0027386 (2001-10-01), Milsom
patent: 2004/0049748 (2004-03-01), Croix
patent: 2004/0049749 (2004-03-01), Croix
Chen, “Path Sensitization In Critical Path Problem”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 12, No. 2, Feb. 1993, pp. 196-207.
Dartu et al., “TETA: Transistor-Level Engine For Timing Analysis”, 35thDesign Automation Conference, 1998, 4 pgs.
Croix et al., “A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis”, 34thDesign Automation Conference, 1997, 4 pgs.
Dartu et al., “Calculating Worst-Case Gate Delays Due To Dominant Capacitance Coupling”, 34thDesign Automation Conference, 1997, 6 pgs.
Lam et al., “Exact Minimum Cycle Times For Finite State Machines”, Proceedings Of The 31stIEEE/ACM Design Automation Conference, Jun. 1994, 6 pgs.
O'Brien et al., “Modeling The Driving-Point Characteristic Of Resistive Interconnect For Accurate Delay Estimation”, IEEE, 1989, pp. 512-515.
Pillage et al., “Asymptotic Waveform Evaluation For Timing Analysis”, IEEE Transactions On Computer Aided Design, vol. 9, No. 4, Apr. 1990, pp. 352-366.
Qian et al., “Modeling The “Effective Capacitance” For The RC Interconnect Of CMOS Gates”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 13, No. 12, Dec. 1994, pp. 1526-1535.
Ratzlaff et al., “RICE: Rapid Interconnect Circuit Evaluation Using AWE”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 13, No. 6, Jun. 1994, pp. 763-776.
Silveira et al., “Efficient Reduced-Order Modeling Of Frequency-Dependent Coupling Inductances Associated With 3-D Interconnect Structures”, 32ndACM/IEEE Design Automation Conference, 1995, 5 pgs.
Dartu et al., “A Gate-Delay Model For High-Speed CMOS Circuits”, 31stACM/IEEE Design Automation Conference, 1994, 5 pgs.
McDonald et al., “Computing Logic-Stage Delays Using Circuit Simulation And Symbolic Elmore Analysis”, 38thACM Design Automation Conference, 2001, pp. 283-288.
Sun et al., “Efficient Timing Analysis For CMOS Circuits Considering Data Dependent Delays”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 17, No. 6, Jun. 1998, pp. 546-552.
Dartu et al., “Performance Computation For Precharacterized CMOS Gates With RC Loads”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 15, No. 5, May 1996, pp. 544-553.
Chen et al., “A New Gate Delay Model For Simultaneous Switching And Its Application”, 38thACM Design Automation Conference, 2001, pp. 289-294.
Arunachalam et al., “CMOS Gate Delay Models For General RLC Loading”, IEEE International Conference On Computer Design, VLSI In Computers And Processors, 1997, 6 pgs.
Yalcin et al, “Fast And Accurate Timing Characterization Using Functional Information”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 20, No. 2, Feb. 2001, pp. 315-331.
Shih et al., “ILLIADS: A Fast Timing And Reliability Simulator For Digital MOS Circuits”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 12, No. 9, Sep. 1993, pp. 1387-1402.
Ngoya et al., “Newton-Raphson Iteration Speed-Up Algorithm For The Solution Of Nonlinear Circuit Equations In General-Purpose CAD Programs”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 16, No. 6, Jun. 1997, pp. 638-644.
Acar et al., “TETA: Transistor-Level Waveform Evaluation For Timing Analysis”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 21, No. 5, May 2002, pp. 605-616.
Devgan et al., “Adaptively Controlled Explicit Simulation”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 13, No. 6, Jun. 1994, pp. 746-762.
Liu et al, “Ftd: An Exact Frequency To Time Domain Conversion For Reduced Order RLC Interconnect Models”, 35thDesign Automation Conference, 1998, 4 pgs.
Bracken et al., Interconnect Simulation With Asymptotic Waveform Evaluation (AWE), IEEE Transactions On Circuits And Systems-1: Fundamental Theory And Applications, vol. 39, No. 11, Nov. 1992, pp. 869-878.
Odabasioglu et al., “PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm”, IEEE, 1997, 8 pgs.
Alpert et al., “RC Delay Metrics For Performance Optimization”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 20, No. 5, May 2001, pp. 571-582.
Ratzlaff et al., “Modeling The RC-Interconnect Effects In A Hierarchical Timing Analyzer”, IEEE Custom Integrated Circuits Conference, 1992, 4 pgs.
Raghavan et al., “A New Nonlinear Driver Model For Interconnect Analysis”, 28thACM/IEEE Design Automation Conference, 1991, pp. 561-566.
Kashyap et al., “An “Effective” Capacitance Based Delay Metric For RC Interconnect”, IEEE, 2000, pp. 229-234.
Kahng et al., “An Analytical Delay Model For RLC Interconnects”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 16, No. 12, Dec. 1997, pp. 1507-1514.
Kam et al., “EDA Challenges Facing Future Microprocessor Design”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 19, No. 12, Dec. 2000, pp. 1498-1506.
Hitchcock et al., “Timing Analysis Of Computer Hardware”, IBM J. Res. Develop., vol. 26, No. 1, Jan. 1982, pp. 100-105.
Darringer et al., “EDA In IBM: Past, Present, And Future”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 19, No. 12, Dec. 2000, pp. 1476-1497.
Kobayashi et al., “Delay Abstraction In Combinational Logic Circuits”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 16, No. 10, Oct. 1997, pp. 1205-1212.
Chatzigeorgiou et al., “A Modeling Technique For CMOS Gates”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 18, No. 5, May 1999, pp. 557-575.
Hirata et al., “Proposal Of A Timing Model For CMOS Logic Gates Driving A CRC π Load”, ACM Conference, 1998, pp. 537-544.
Jen et al., “A Compact And Unified MOS DC Current Model With Highly Continuous Conductances For Low-Voltage IC's”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 17, No. 2, Feb. 1998, pp. 169-172.
Hafed et al., “Delay And Current Estimation In A CMOS Inverter With An RC Load”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 20, No. 1, Jan. 2001, pp. 80-89.
Korshak et al., 

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