Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2011-07-26
2011-07-26
Barnie, Rexford N (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S038000
Reexamination Certificate
active
07986160
ABSTRACT:
A PLD includes at least one IP block or circuit, and at least one I/O block or circuit. The performance of the at least one IP block is adjusted in order to meet at least one performance characteristic by changing a supply level of the at least one IP block, by adjusting at least one body bias level of the IP block, or both. The performance of the at least one I/O block is adjusted by changing a supply level of the at least one I/O block, by adjusting at least one body bias level of the I/O block, or both.
REFERENCES:
patent: 5057704 (1991-10-01), Koyanagi
patent: 5600264 (1997-02-01), Duong et al.
patent: 5610533 (1997-03-01), Arimoto et al.
patent: 5631606 (1997-05-01), Tran
patent: 5661685 (1997-08-01), Lee et al.
patent: 5686752 (1997-11-01), Ishimura et al.
patent: 5781062 (1998-07-01), Mashiko et al.
patent: 6157691 (2000-12-01), Wei
patent: 6366128 (2002-04-01), Ghia et al.
patent: 6583646 (2003-06-01), Patel et al.
patent: 6650141 (2003-11-01), Agrawal et al.
patent: 7002397 (2006-02-01), Kubo et al.
patent: 7026840 (2006-04-01), May et al.
patent: 7080270 (2006-07-01), Yokozeki et al.
patent: 7548091 (2009-06-01), Liu
patent: 2002/0000831 (2002-01-01), Smith
patent: 2003/0001633 (2003-01-01), Gresham
patent: 2003/0208611 (2003-11-01), Weber et al.
patent: 2006/0190755 (2006-08-01), Kim
patent: 2008/0045166 (2008-02-01), Koch et al.
Tsuguo Kobayashi et al., “Self-Adjusting Threshold Voltage Scheme (SATS) for Low-Voltage High Speed Operation,” IEEE 1994 Custom Integrated Circuits Conference, pp. 271-274 (1994).
Tadahiro Kuroda et al., “FA 10.3: A 0.9V 150MHz 10mW 4mm22-D Discrete Cosine Transform Core Porcessor with Variable-Threshold-Voltage Scheme,” ISSCC96, pp. 166-68 (1996).
Masayuki Miyazaki et al., “WP 25.6: A 1000-MIPS/W Microprocessor using Speed-Adaptive Threshold-Voltage CMOS with Forward Bias,” 2000 IEEE Int'l Solid-State Circuits Conference, 3 pp. (2000).
Masayuki Miyazaki et al., “A Delay Distribution Squeezing Scheme with Speed-Adaptive Threshold-Voltage CMOS (SA-Vt CMOS) for Low Voltage LSIs,” 6 pp. (1998).
Sherif T. Eid et al., “A Microcontroller-Based PVT Control System for a 65nm 72Mb Synchronous SRAM,” 2010 ISSCC 184-85.
James Tschanz et al., “A 45nm Resilient and Adaptive Microprocessor Core for Dynamic Variation Tolerance,” 2010 ISSCC 282-83.
Jinuk Luke Shin et al., “A 40nm 16-Core 128-Thread CMT SPARC SoC Processor,” 2010 ISSCC 98-99.
Tae-Hyoung Kim et al., “Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits,” 43 IEEE Journal of Solid-State Circuits 874-80 (2008).
Hoang Tim Tri
Shumarayev Sergey
Altera Corporation
Barnie Rexford N
Law Offices of Maximilian R. Peterson
Tran Thienvu V
LandOfFree
Apparatus and methods for adjusting performance... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and methods for adjusting performance..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and methods for adjusting performance... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2636419