Apparatus and methodology for an input port scheduler

Details Apparatus and methodology for an input port scheduler Apparatus and methodology for an input port scheduler

2007-09-11

2007-09-11

Lane, Jack A. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S005000, C711S154000, C709S214000, C709S216000, C709S217000, C709S220000, C709S226000, C709S232000, C709S233000, C709S251000

Reexamination Certificate

active

10434001

ABSTRACT:
A scheduler to manage the reading activity of a plurality of read hubs is described. Each read hub is capable of reading a piece of a packet from a different memory bank within a same cycle of operation so that pieces of different packets can be read from the memory banks within the same cycle of operation. The scheduler: 1) defines each read hub as an active read hub or inactive read hub, wherein an active read hub is engaged to read at least one packet from the memory banks and an inactive read hub is not so engaged; 2) defines each active read hub as a low speed mode read hub or a high speed mode read hub, wherein, a first packet read by a high speed mode read hub is read from the memory banks at a faster rate than a second packet read by a low speed mode read hub; and, 3) dynamically changes the number of active read hubs, the number of low speed mode read hubs and the number of high speed mode read hubs in light of traffic conditions.

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