Apparatus and method with improved power-down mode

Details Apparatus and method with improved power-down mode Apparatus and method with improved power-down mode

1998-10-20

2000-07-11

Ray, Gopal C.

Electrical computers and digital processing systems: support

Computer power control

Power conservation

713300, 713601, G06F 108, G06F 132, G06F 900

Patent

active

060888067

ABSTRACT:
A power-down circuit (72) in a lap-top computer (10) cooperates with a separate monitor circuit (80) in each of a plurality of modules (68, 74, 76) that a video-display-controller integrated circuit (36) includes. In response to various stimuli, decoding logic (78) in the power-down circuit sends respective power-down-request signals to the various monitor circuits request permission to suppress application of respective clock signals to them. If a module's operational circuitry (82) is in a state in which clock removal is safe, the monitor circuit (80) responds with an acknowledgment signal, and the power-down circuit (72) causes a clock generator to interpret application of clock signals to the respective module (68). The monitor circuit (80) may additionally detect circumstances in which removing the clock signal from the operational circuitry (82) is safe only if the clock signal can subsequently be re-applied rapidly. In those circumstances, the monitor circuit (80) generates an idle signal that causes the power-down circuit (72) to stop clocking the associated operational circuitry but continue clocking the monitor circuit. In this way, the monitor circuit can keep operating so as to detect circumstances that will necessitate re-starting operational-circuit clocking. When it detects such a condition, it rapidly de-asserts the idle signal so that the clock signal is rapidly re-applied to the associated operational circuit.

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