Apparatus and method using volatile lock and lock-down registers

Details Apparatus and method using volatile lock and lock-down registers Apparatus and method using volatile lock and lock-down registers

1998-05-11

2000-11-28

Nguyen, Hiep T.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711103, 711152, 711173, 36518533, G06F 1214

Patent

active

061548197

ABSTRACT:
An apparatus for protecting memory blocks in a block-based flash Erasable Programmable Read Only Memory (EPROM) device is disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register and transmits a write protect signal and a volatile lock-down register are coupled to a lockable block in the volatile memory array. A hardware override line is coupled to both the lock register and the lock-down register. The hardware override line temporarily overrides operation of the lock-down register when it transmits a signal at a first logic state. The lock down register may be used to prevent programming of an associated lock register. The lock registers and lock down registers may be embodied in static access memory (SRAM) circuits. A command buffer may be operable to transmit a two cycle command including a first command specifying whether a lock configuration is to be changed and a second command specifying whether a block is to be placed in a lock state, an unlock state, or locked down state. The lock down registers may be capable of being set to lock down only once during a period in which the apparatus is powered up.

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