Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2005-12-13
2005-12-13
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S167000, C710S058000
Reexamination Certificate
active
06976121
ABSTRACT:
An apparatus and a method to track command signal occurrence for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes an interface to couple to a data bus, the data bus to transfer data between the interface and one or more memory devices, and a logic unit to generate a command occurrence signal to identify when a command signal is issued, wherein a set of data transfer operations on one of the one or more memory devices are completed in response to the command occurrence signal, a transition of a flag signal, and a chip select signal corresponding to the one memory device. Other embodiments have been claimed and described.
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David Howard S.
Khandekar Narendra S.
Williams Michael W.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Peikari B. James
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