Apparatus and method to reduce instruction address storage in a

Details Apparatus and method to reduce instruction address storage in a Apparatus and method to reduce instruction address storage in a

1996-06-18

1998-06-09

Lim, Krisna

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

395382, 395383, 395386, 711213, G06F 1206

Patent

active

057652201

ABSTRACT:
A system for storing addresses of instructions being executed in a processor by storing an address of a first instruction in a line of cache or memory in an instruction address queue. With each instruction fetched from the line, the system stores an index into the instruction address queue for the entry that contains the address of the first instruction in the line. For each instruction fetched from the line, the system also stores an offset value indicating the relative position of the instruction within the line. To determine the address of an instruction, the processor uses the index to retrieve the address of the first instruction of the line from the instruction address queue, and then appends the offset value to the end of the value retrieved from the instruction address queue to form the actual memory address of the instruction.

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Lightner, Bruce D., "The SPARC Lightning Processor", Hot Chips II, 1990 Symposium on High Performance Chips.

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