Apparatus and method to improve primary memory latencies using a

Details Apparatus and method to improve primary memory latencies using a Apparatus and method to improve primary memory latencies using a

1996-05-31

1999-01-12

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

395859, 395860, 711117, 711158, G06F 1208

Patent

active

058601171

ABSTRACT:
A central processing unit of a computer includes an external cache controller and a primary memory controller. The external cache controller generates a primary memory read request and a primary memory write request in response to an external cache miss. The primary memory controller includes an address queue, an eviction buffer, and an eviction buffer logic circuit. The eviction buffer logic circuit selectively stores the primary memory write request in the eviction buffer and stores the primary memory read request in the address queue. When subsequent primary memory read requests are received at the primary memory controller, the eviction buffer logic circuit routes them to the address queue. The primary memory write request in the eviction buffer is passed to the address queue when the eviction buffer logic circuit identifies an empty queue, meaning there are no pending primary memory write requests. The data in the eviction buffer is also sent to the address queue when a new primary memory write request is received at the eviction buffer logic circuit.

REFERENCES:
patent: 5404483 (1995-04-01), Stamm et al.
patent: 5434993 (1995-07-01), Liencres et al.
patent: 5553270 (1996-09-01), Rosenbluth
patent: 5566317 (1996-10-01), Treiber et al.
patent: 5649157 (1997-07-01), Williams

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