Apparatus and method to guarantee forward progress in execution

Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

709100, G06F 900

Patent

active

061050512

ABSTRACT:
A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

REFERENCES:
patent: 3373408 (1968-03-01), Ling
patent: 3566357 (1971-02-01), Ling
patent: 3568173 (1971-03-01), Klinger
patent: 3594732 (1971-07-01), Mendelson et al.
patent: 3728692 (1973-04-01), Fennel, Jr.
patent: 3771138 (1973-11-01), Celtruda et al.
patent: 3916383 (1975-10-01), Malcolm
patent: 3980991 (1976-09-01), Mercurio
patent: 3980992 (1976-09-01), Levy et al.
patent: 4047161 (1977-09-01), Davis
patent: 4084228 (1978-04-01), Dufond et al.
patent: 4229790 (1980-10-01), Gilliland et al.
patent: 4320453 (1982-03-01), Roberts et al.
patent: 4384324 (1983-05-01), Kim et al.
patent: 4493020 (1985-01-01), Kim et al.
patent: 4532587 (1985-07-01), Roskell et al.
patent: 4590555 (1986-05-01), Bourrez
patent: 4692861 (1987-09-01), May
patent: 4704678 (1987-11-01), May
patent: 4829425 (1989-05-01), Bain, Jr. et al.
patent: 4853849 (1989-08-01), Bain, Jr. et al.
patent: 5050070 (1991-09-01), Chastain et al.
patent: 5079725 (1992-01-01), Geer et al.
patent: 5103394 (1992-04-01), Blasciak
patent: 5148536 (1992-09-01), Witek et al.
patent: 5159686 (1992-10-01), Chastain et al.
patent: 5179702 (1993-01-01), Spix et al.
patent: 5197138 (1993-03-01), Hobbs et al.
patent: 5287508 (1994-02-01), Hejna, Jr. et al.
patent: 5339415 (1994-08-01), Strout, II et al.
patent: 5353418 (1994-10-01), Nikhil et al.
patent: 5357617 (1994-10-01), Davis et al.
patent: 5361337 (1994-11-01), Okin
patent: 5404469 (1995-04-01), Chung et al.
patent: 5408671 (1995-04-01), Tanaka
patent: 5430850 (1995-07-01), Papadopoulos et al.
patent: 5471593 (1995-11-01), Branigin
patent: 5490272 (1996-02-01), Mathis et al.
patent: 5499349 (1996-03-01), Nikhil et al.
patent: 5515538 (1996-05-01), Kleiman
patent: 5530866 (1996-06-01), Koblenz et al.
patent: 5535361 (1996-07-01), Hirata et al.
patent: 5553305 (1996-09-01), Gregor et al.
patent: 5574939 (1996-11-01), Keckler et al.
patent: 5613114 (1997-03-01), Anderson et al.
patent: 5630136 (1997-05-01), Davidson et al.
IBM Technical Disclosure Bulletin, vol. 39, No. 08, Aug. 1996, pp. 113-116, Entitled "Algorithm for Instruction Cache Arbitration Among Multiple Instruction Streams".
Eickemeyer et al, "Evaluation of Multithreaded Uniprocessors for Commercial Application Enviornments", 23rd International Symposium on Computer Architecture, pp. 203-212, May 1996.
Song P., "Multithreading Comes of Age", Microdesign Resources, Microprocessor Report, pp. 13-18, Jul. 14, 1997.
"Analytic Performance Modeling for the Spectrum of Multithreaded Processor Archtecture", Pradeep K. Dubey, 1995 IEEE.
"Dynamic Scheduling In RISC Architecture", A. Bolychevsky, IEE Proc-computer, Digit. Tech. No. 5, Sep. 1996.
"Unstable Threads Kernel Interface for minimizing the Overhead of Thread Switching", Shigekazu Inohara et al., IEEE 1993.
Elkateeb, Ali et al; IEEE Pacific Rim Conference 1993, pp. 141-144, "A Task Allocation by Priority Strategy for RISC Architecture Supported with Non-Overlapped Multiple Register Set: A Complexity Study".
Fiske, Stuart et al; Future Generation Computer Systems II, Oct. 1995, No. 6, pp. 503-518, "Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors".
Aschenbrenner, R. et al, "Intrinsic Multiprocessing", AFIPS Conference Proceedings, vol. 30, 1967 Spring Joint Computer Conference, pp. 81-86.
Hatch, T. F. Jr. et al, "Hardware/Software Interaction on the Honeywell Model 8200", AFIPS Confe Proceedings, vol. 33, Part 1, 1968, Fall Joint Computer Conference, pp. 891-901.
Foster, C. C., "Uncoupling Central Processor and Storage Device Speeds", The Computer Journal, vol. 14, No. 1, pp. 45-48.
Anderson, D. W. et al, The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling IBM Journal of Research and Development, vol. 11, 1967, pp. 8-24.
Cook, Robert W. et al, "System Design of a Dynamic Microprocessor", IEEE Transactions on Compute vol. C-19, No. 3, Mar. 1970, pp. 213-222.
Cull, Thomas C., The Honeywell 8200, Datamation, vol. 11, No. 7, Jul. 1965, pp. 90-91.
Nisenoff, N., "Scratchpad Memories at Honeywell: Past, Present, and Future" AFIPS Conference Proceedings, vol. 27, Part 1, 1965, Fall Joint Computer Conference, pp. 679-688.
"Honeywell 800 System", from the collecitons of the Univeristy of Toledo Libraries, pp. 0-42.
Dreyfus, P., "Programming Design Features of the Gamma 60 Computer", Proceedings of the Eastern Joint Computer Conference, Dec. 3-5, 1958, pp. 174-181.
Miller, Edward F. Jr., "A Mulitple-Stream Registerless Shared-Resource Processor", IEEE Transactions on Computers, vol. C-23, No. 3, Mar. 1974, pp. 277-285.
Culler, Arvind and David E., "Dataflow Architectures", Annual Review Computer Science, 1986, pp. 225-253.
Buehrer, Richard et al, "Incorporating Data Flow Ideas into von Neumann Processors for Parallel Execution", IEEE Transactions on Computers, vol. C-36, No. 12, Dec. 1987, pp. 1515-1522.
Halstead, Robert H. Jr. et al, "MASA: A Multithreaded Processor Architecture for Parallel Symbol Computing", 15th Annual International Symposium on Computer Architecture, 1988, pp. 443-451.
Agarwal, A. et al, "April: A Processor Architecture for Multiprocessing", Proceedings of the 17 Symposium on Computer Architecture, May 1990, pp. 104-114.
Agarwal, A., "Analysis of Cache Performance for Operating Systems and Multiprogramming", Dissertation Abstracts International, vol. 48, No. 7, Jan. 1988, pp. 2024-B.
Dally, William J. et al, "Architecture of a Message-Driven Processor", 14th Annual Internationa Symposium on Computer Architecture, Jun. 1987, pp. 189-196.
Arvind et al, "A Critique of Multiprocessing von Neumann Style", Proceedings of the 10th ACM International Symposium on Computer Architecture, Jun. 1983, pp. 426-436.
Flynn, Michael J. et al, An Unconventional Computer Architecture: Shared Resource Multiproces Computer, Mar./Apr. 1972, pp. 20-28.
Shar, Leonard E. et al, "A Multiminiprocessor System Implemented Through Pipelining", Computer Feb. 1974, pp. 42-51.
Kaminski, W. J. et al, "Developing a Multiple-Instruction-Stream Single-Chip Processor", Computer, Dec. 1979, pp. 66-76.
Konsek, Marian B. et al, "Context Switching With Multiple Register Windows: A RISC Performance Study", Stanford Technical Report No. UIUCDCS-R-87-1377, Oct. 1987, pp. 0-32.
Kishi, Masasuke et al, "DDDP: A Distributed Data Driven Processor", Proceedings of 10th International Symposium on Computer Architecture, 1983, pp. 236-242.
Ohr, Stephen "RISC Machines", Electronic Design, vol. 33, Jan. 10, 1985, pp. 174-190.
Ragan-Kelley, Robert et al, "Applying RISC Theory to a Large Computer", Computer Design, vol. 22, No. 13, Nov. 1983, pp. 191-198.
Mayhew, David et al, "Overlapping Register Windows with Transparent Spill and In-Line Subroutine Expansion", Conference Proceedings IEEE Southeastcon '87, Apr. 1987, pp. 627-630.
Markoff, John "RISC Chips--RISC Means Longer Programs but Faster Execution", BYTE, vol. 9, No. 12, Dec. 1984, pp. 191-206.
Seitz, Charles L., "The Cosmic Cube", Communications of the ACM, vol. 28, No. 1, Jan. 1985, pp. 22-33.
Smith, Bob "Chips in Transition", PC Tech Journal, vol. 4, No. 4, Apr. 1986, pp. 56-63.
Kuehn, James T. et al, "The

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Apparatus and method to guarantee forward progress in execution does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus and method to guarantee forward progress in execution , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method to guarantee forward progress in execution will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2018419

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.