Electrical computers and digital processing systems: processing – Processing control – Mode switch or change
Reexamination Certificate
1998-10-30
2002-05-21
Follansbee, John A. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing control
Mode switch or change
C712S043000, C712S228000
Reexamination Certificate
active
06393556
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to computer processors, and more particularly, to changing the privilege level of a computer processor.
2. Description of Related Art
Computers and many other types of machines are engineered around a “processor.” A processor is an integrated circuit that executes programmed instructions stored in the machine's memory. Some processors “pipeline” instructions. The processor reads instructions from memory and feeds them into one end of the pipeline. The pipeline is made of several “stages,” each stage performing some function necessary or desirable to process instructions before passing the instruction to the next stage. For instance, the first stage might fetch the instruction, the next stage might decode the fetched instruction, and the next stage might execute the decoded instruction. Each stage of the pipeline typically moves the instruction closer to completion. A pipeline therefore has the tremendous advantage that, while one part of the pipeline is working on a first instruction, a second part of the pipeline can be working on a second instruction. Thus, more than one instruction can be processed at a time, thereby increasing the rate at which instructions can be executed in a given time period. This, in turn, increases the processor throughput.
In order to effect security features and provide multi-user capability in processors, including pipelined processors, operating system software needs to prevent the user from performing certain dangerous (insecure) operations. For example, operating system instructions may be assigned one privilege level, while application program instructions may be assigned a lower privilege level. Thus, the operating system instruction would have access to some system resources that the application program instructions would not have access to. Privilege levels can sometimes be dynamic in the sense that they can occasionally change.
To accomplish this, the operating system software assigns a privilege level to the processor. A “current privilege level” (“CPL”) for the processor is normally maintained in the processor's architectural register set. Changing the processor's privilege level, however, is often a costly function when measured by the number of processor clock cycles needed to perform the operation. Known processors empty, or “flush” the pipeline on every operation that changes the privilege level, when the instruction changing the privilege level executes and the CPL is updated. This insures that the proper privilege level is applied to instructions in the pipeline, but results in reduced processor performance.
FIG. 1
conceptually illustrates a pipeline
10
of a prior art processor having, for purposes of illustration, four stages: fetch
11
, decode
12
, execute
13
, and retire
14
. Pipelines of prior art processors, such as the pipeline
10
illustrated in
FIG. 1
, operate at a single privilege level at any given time. Hence, at time T
1
, the pipeline
10
is operating at a first privilege level assigned by the operating system, and implemented via a previously executed instruction. A first instruction
21
is fetched from memory during the fetch stage
11
of the pipeline
10
at time T
1
. Assume that the first instruction
21
will direct the processor to change the CPL to a different privilege level.
At time T
2
, the first instruction
11
proceeds to the decode stage
12
, and a second instruction
22
is fetched. The first and second instructions
21
,
22
continue down the pipeline
10
, and third and fourth instructions
23
,
24
enter the pipeline during time T
3
and T
4
. When the first instruction
21
is retired (time T
4
), the CPL of the pipeline
10
is updated to the new privilege level as directed by the first instruction
21
. When the first instruction
21
is retired, or exits the pipeline, to insure that the subsequent instructions
22
,
23
,
24
are executed at the proper privilege level, the pipeline
10
is flushed, and the work done on the second, third, and fourth instructions
22
,
23
,
24
during time periods T
2
-T
4
is lost. The second instruction
22
restarts the pipeline
10
at time T
5
, and is not retired until time T
8
.
Thus, when the privilege level of a prior art pipeline is changed, many of the advantages gained by pipelining instructions are lost. The present invention addresses these, and other shortcomings of the prior art.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a processor maintains an architectural privilege level that is assigned a first privilege level. A method of pipelining instructions in such a processor includes processing a first instruction that directs the processor to change the architectural privilege level to a second privilege level, and flushing any subsequent instructions from the pipeline prior to changing the architectural privilege level to the second privilege level.
In another aspect of the invention, a processor configured to pipeline instructions includes a first memory in which a first privilege level is recorded, a second memory storing a plurality of instructions, and a pipeline including a plurality of processing stages. The processor is adapted to fetch a first instruction from the second memory and determine whether the first instruction requires the first privilege level be changed to a second privilege level, and in response thereto, flush any subsequent instructions from the pipeline before recording the second privilege level in the first memory.
REFERENCES:
patent: 5144551 (1992-09-01), Cepulis
patent: 5487156 (1996-01-01), Popescu et al.
patent: 5692170 (1997-11-01), Isaman
Blakely , Sokoloff, Taylor & Zafman LLP
Follansbee John A.
Intel Corporation
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