Apparatus and method to balance set-up and hold times

Details Apparatus and method to balance set-up and hold times Apparatus and method to balance set-up and hold times

2008-04-01

2008-04-01

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

Reexamination Certificate

active

10832528

ABSTRACT:
A circuit for data/clock deskewing includes a data delay circuit and a clock circuit. The data delay circuit is arranged to select a delay for the data signal responsive to a data delay signal. The clock circuit is arranged to provide an even clock signal and an odd clock signal, and to select one of them responsive to a clock select signal. Also, two delayed versions of the selected clock signal are provided. The data latching circuit is arranged to latch the delayed data signal with the selected clock and with the two delayed versions of the selected clock signal. Further, the latched data signals are employed to deskew the clock and data signals such that set-up and hold times are substantially optimized under jittery conditions.

REFERENCES:
patent: 5258660 (1993-11-01), Nelson et al.
patent: 5313501 (1994-05-01), Thacker
patent: 5467464 (1995-11-01), Oprescu et al.
patent: 5768283 (1998-06-01), Chaney
Altera Corporation, “Using LVDS in APEX 20KE Devices”, Altera, White Paper, Jan. 2000, Version 1, pp. 1-18.

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