Apparatus and method of synchronizing two logic blocks operating

Details Apparatus and method of synchronizing two logic blocks operating Apparatus and method of synchronizing two logic blocks operating

1997-09-05

2000-09-12

Bocure, Tesfaldet

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375377, H04L 700

Patent

active

061188352

ABSTRACT:
An apparatus and method employs a First In, First Out (FIFO) buffer to separate a first logic block operating at a first rate, such as 33.75 MHz, from a second logic block operating at a second rate, such as 27 MHz, which is lower than the first rate. The dual port FIFO operates with asynchronous Read and Write ports, and the Write port controls the input of data from the first logic block at the first rate to the FIFO. The FIFO provides a value indicating that the FIFO is full. Enablement of the Read port is based upon the presence of data in the FIFO and a synchronization signal for the data. Once enabled, the data is transferred from the FIFO to the second logic block at the second rate. A flag value of the FIFO is set when the FIFO buffer is full, and is used by the first logic block to interrupt data transfer into the FIFO at the first rate to allow data provided at the FIFO output at the second rate to empty the FIFO buffer.

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