Apparatus and method of snooping processors and look-aside cache

Details Apparatus and method of snooping processors and look-aside cache Apparatus and method of snooping processors and look-aside cache

1996-08-26

1999-02-23

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711124, 711123, 711122, 711141, 711205, 711207, G06F 1300

Patent

active

058754695

ABSTRACT:
The present invention provides a method and apparatus for providing memory coherency among an L1 and an L2 cache memory devices and a main memory device. In an embodiment of the invention, a memory controller generates an address snoop for locating modified copies of a data residing in the main memory. As a result of the snoop, the memory controller is notified as to whether a modified copy of the data is in the cache memory devices. If both cache memory devices have a modified copy of the data, the modified copy in the L2 cache will not be allowed to be transferred since modified copies of data in the L1 cache memory are considered to always be the most recent copies of the data. Thus, if the L1 cache memory is unable to transfer the data, The memory controller will continue to snoop the address until the L1 cache memory transfers the data. If, however, there is only one copy of the modified data and it resides in the L2 cache memory device, the copy will be allowed to be transferred to the memory controller.

REFERENCES:
patent: 5091846 (1992-02-01), Sachs et al.
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patent: 5479630 (1995-12-01), Kiuian
patent: 5553265 (1996-09-01), Abato et al.
patent: 5561779 (1996-10-01), Jackson et al.

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