Apparatus and method of performing AES Rijndael algorithm

Cryptography – Particular algorithmic function encoding

Reexamination Certificate

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Reexamination Certificate

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07639797

ABSTRACT:
An encryption and decryption apparatus includes a round key generator generating at least one round key for iterative operations in each of a plurality of rounds using an input key for one of the encryption and decryption; an initial round key adder receiving a plurality of divided parts of an input data, consecutively receiving a plurality of parts of an initial round key which is output from the round key generator for an initial round and corresponds to each of the divided input data, and adding the input data and the corresponding part of the initial round key; a first operator receiving a first data which is output from the initial round key adder and a part of the round key which is output from the round key generator and performing operations for one of the encryption and decryption; a second operator receiving a second data which is output from the initial round key adder and another part of the round key which is output from the round key generator, and performing operations for one of the encryption and decryption; and a register part temporarily storing the first data which is output from the first operator and the second data which is output from the second operator, inputting the first and second data to the first and second operators, respectively, for operations of a next round among the plurality of the rounds, and outputting an encrypted or decrypted data when the plurality of the rounds are completed.

REFERENCES:
patent: 2003/0198345 (2003-10-01), Van Buer
patent: 2004/0047466 (2004-03-01), Feldman et al.
patent: 2004/0202317 (2004-10-01), Demjanenko et al.
patent: 2006/0109981 (2006-05-01), Sexton
“A Method to Implement Block Ciphers in Reconfigurable Hardware and its Application to Fast and Compact AES Rijndael” Standaert et al. Published Feb. 23-25, 2003 © 2003 ACM.
“Unlocking the Design Secrets of a 2.29GB/s Rijndael Processor” Schaumont et al. Published Jun. 10-14, 2002 © 2002 ACM.
“AES and the Cryptonite Crypto Processor” Oliva et al. Published Oct. 30-Nov. 1, 2003 © 2003 ACM.
Wikipedia article for “64-bit” published Nov. 16, 2003 http://en.wikipedia.org/w/index.php?title=64-bit&oldid=1917574.
A. Panato et al. “A Low Device Occupation IP to Implement Rijndael Algorithm” Proceedings of the Design, Automation, and Test in Europe Conference and Exhibition. © 2003 IEEE. (6 pages).
A. Satoh et al. “A Compact Rijndael Hardware Architecture with S-Box Optimization” © 2001 Springer-Verlag Berlin Heidelberg. pp. 239-254.

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