Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-06-08
2001-05-15
Beausoleil, Robert (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S120000, C710S031000
Reexamination Certificate
active
06233641
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to routing of bus commands between computer systems and expansion slots and cards.
BACKGROUND OF THE INVENTION
Computer systems typically include expansion slots which permit the enhancement of the functionality of the computer system by the inclusion of additional circuitry. These expansion slots are typically connected via an expansion bus to the processor complex, i.e., the processor and its associated circuitry. For example, an input/output adapter (IOA) can be added to a computer system to allow external receipt and transmission of data, e.g., from a computer network.
Several standards have evolved for expansion slots and expansion cards. Two well known standards are the ISA standard and Microchannel standard, both of which define particular arrangements of the contacts in the expansion slots and the edge of the expansion cards, as well as defining protocols for communication between a compatible expansion card and the computer system.
A more recent standard is the PCI standard, which is intended for use in many computing environments in place of or in addition to the older ISA and Microchannel standards. The PCI architecture includes, in addition to other features supported by earlier standards, a definition for a PCI bridge. A PCI bridge connects between a “primary” PCI expansion bus at the side of the bridge closest to the processor, and a “secondary” bus on the other side of the bridge; the secondary bus may be a PCI, ISA, Microchannel, or other type of expansion bus. A PCI bridge might be used where there are not enough slots in a computer system to connect all desired expansion cards, and an additional slot or slots is desired; the additional slots can be provided on the secondary bus. A PCI bridge may also be used to interface the PCI bus on a computer system to older ISA or Microchannel expansion cards connected to a secondary ISA or Microchannel bus, which is bridged to the primary PCI bus.
Additionally, a PCI bridge may be used to provide a “hot swap” capability: specifically, the presence of the bridge permits power to be applied to and removed from the secondary bus independently from the primary bus. Accordingly, the expansion cards on the secondary bus can be replaced while the computer system remains on, by removing power from the secondary bus, replacing the card on the secondary bus, and then reapplying power to the secondary bus. In computing systems which support hot swapping of some or all of the expansion cards, each expansion card may be on a separate secondary bus bridged to the primary PCI bus, to permit the expansion cards to be individually hot-swapped without power-down of any other expansion cards.
The PCI standard specifies that a PCI bridge provide address mapping registers which can be configured from the primary bus. The values in the address mapping registers define an address range within the entire address space of the primary bus. When a memory or input/output (I/O) command is delivered to the primary bus by the processor or other circuitry connected to the primary bus, the bridge compares the address of the command to the address range defined by the address mapping registers in the bridge. If the address of the command falls within the address range defined by the mapping registers, then the memory or I/O command is passed through the bridge to the secondary bus connected to the bridge. Furthermore, when a memory or I/O command is delivered to the secondary bus connected to the bridge, the bridge compares the address of the command to the address range defined by the mapping registers, and if the address of the command is not within the address range, the command is passed through the bridge to the primary bus connected to the bridge.
Many computing systems include expansion cards which access or communicate with both the processor complex and other expansion cards in the computer system. If an expansion card is not on the same secondary bus as the expansion card that it accesses, e.g., where each card is on its own secondary bus to facilitate hot swapping, this can result in excessive traffic between the expansion cards via the primary PCI bus, introducing latency and making the expansion cards operate in less than an optimal manner.
Therefore, a significant need continues to exist for an improved manner of routing commands between and among computer systems and expansion slots or cards.
SUMMARY OF THE INVENTION
The invention addresses these and other problems associated with the prior art by providing an apparatus and method of routing commands between a computer system and an expansion slot or card.
In accordance with the present invention, a primary bus and first and second secondary busses are interconnected by a routing circuit. The routing circuit functions as a bridge between the primary bus and each of the first and second secondary busses, respectively, by associating each secondary bus with an address range, and forwarding a command received from the primary bus to a secondary bus mapped to an address range including the address of the command. Furthermore, the routing circuit forwards from a secondary bus, commands intended for the primary bus. In addition, the routing circuit directly routes to the second secondary bus, a command received from the first secondary bus addressed for the second secondary bus, without use of the primary bus. As a result, traffic and latency on the primary bus is reduced and efficiency is increased.
In the specific embodiment described below, the routing circuit incorporates control registers specifying address ranges on the primary bus which map to the first and second secondary bus, and a routing table specifying address ranges on each secondary bus which map to the primary bus or to other secondary busses. A control circuit compares the address of a command received from the primary bus to the control registers, to identify the secondary bus (if any) to which the command should be forwarded. Furthermore, the control circuit compares the address of a command received from the secondary bus, to the routing address ranges in the routing table, to determine the bus (if any) to which the command is to be directed. A command received from the first secondary bus with an address in the address range mapped in the routing table to the second secondary bus, is directly routed to the second secondary bus without use of the primary bus. Furthermore, a command received from the second secondary bus with an address in the address range of the first secondary bus, is directly routed to the first secondary bus without use of the primary bus.
In this specific embodiment, there are eight secondary busses, each connected to the routing circuit. The routing table includes entries specifying, for each secondary bus, address ranges which map to any or all of the other secondary busses and the primary bus. A command from a secondary bus with an address in one of the ranges specified in entries for that secondary bus, is directly routed to the bus mapped by the address range.
The routing table entries further specify an address offset to be applied to forwarded commands. Accordingly, a command from a secondary bus with an address in a range associated with an address offset, is modified by the control circuit using the address offset, to have a new address, and then directly routed to the bus mapped by the address range.
The routing table entries also include additional information, such as whether and to what extent a memory read command routed through the routing circuit to a destination bus, should be expanded to pre-fetch additional memory locations not initially requested by the command. The routing table entries further describe different pre-fetch actions to be performed for read operations of different sizes. Further, the routing table entries identify whether and to what extent multiple memory write commands to the same destination bus routed through the routing circuit should be buffered and combined into a single write command of greater size.
Graham Charles Scott
Lambeth Shawn Michael
Moertl Daniel Frank
Movall Paul Edward
Beausoleil Robert
International Business Machines - Corporation
Phan Raymond N
Wood Herron & Evans L.L.P.
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