Apparatus and method of maintaining cache coherency in a multi-p

Details Apparatus and method of maintaining cache coherency in a multi-p Apparatus and method of maintaining cache coherency in a multi-p

1998-02-17

2000-01-25

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711 3, 711118, 711123, 711144, 711146, 711154, 711155, 711210, G06F 1200, G06F 1300

Patent

active

060187913

ABSTRACT:
A multi-processor computer system with clustered processing units uses a cache coherency protocol having a "recent" coherency state to indicate that a particular cache block containing a valid copy of a value (instruction or data) was the most recently accessed block out of a group of cache blocks in different caches (but at the same cache level) that share valid copies of the value. The "recent" state can advantageously be used to implement optimized memory operations such as intervention, by sourcing the value from the cache block in the "recent" state, as opposed to sourcing the value from system memory (RAM), which would be a slower operation. In an exemplary implementation, the hierarchy has two cache levels supporting a given processing unit cluster; the "recent" state can be applied to a plurality of caches at the first level (each associated with a different processing unit cluster), and the "recent" state can further be applied to one of the caches at the second level.

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