Apparatus and method of LSI timing degradation simulation

Details Apparatus and method of LSI timing degradation simulation Apparatus and method of LSI timing degradation simulation

1997-08-27

1999-10-26

Teska, Kevin J.

39550041, 39550007, G06F 9455

Patent

active

059742470

ABSTRACT:
An apparatus and method of simulating the operation of an LSI after degradation is provided for predicting actual LSI degradation with time at the design stage, so as to prevent the LSI specification from becoming excessively reliable. A reliability library generation device drives a circuit reliability simulator and generates a reliability library which shows the dependence of the property degradation degree of each circuit cell on predetermined operational conditions. A cell delay degradation estimation means estimates the delay degradation degree with time of each circuit cell which composes a target LSI, by referring to the reliability library. An LSI timing degradation estimation means estimates the delay of each circuit cell in the target LSI which has been degraded with time, based on the delay degradation degree of each circuit cell, and generates an after-degradation LSI timing. A logic simulator simulates the operation of an LSI after degradation, based on the after-degradation LSI timing, so that the timing degradation of each signal path in the target LSI can be accurately expressed in conformation to real operation.

REFERENCES:
patent: 5508632 (1996-04-01), Shimizu
patent: 5533197 (1996-07-01), Moran et al.
patent: 5600578 (1997-02-01), Fang et al.
patent: 5634001 (1997-05-01), Mittl et al.
T. Goodman et al., "High Speed Electrical Characterization and Simulation of a Pin Grid Array Package ", IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part B, vol. 18, No. 1, Feb. 1995, pp. 163-167.
H. Yonezawa et al., "Ratio Based Hot-Carrier Degradation Modeling for Aged Timing Simulation of Millions of Transistors Digital Circuits", IEDM '98 Technical Digest., International Electron Devices Meeting, 1998, pp. 93-96.
R.H. Tu, et al., "Berkeley Reliability Tools-BERT", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, No. 10, Oct. 1993, pp. 1524-1534.
Cadence Design Systems, "Cadence Standard Parasitic format (SPF)", Cadence Standard Parasitic Format (SPF) Specification, Version C1.3, Sep. 16, 1993, pp. 8-20.
Open Verilog International, "Standard Delay Format Specification", Standard Delay Format Specification, Version 3.0, May 1995, pp. 3-23.

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