Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-10-29
2003-06-24
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06584599
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a layout generating apparatus and a layout generating method of a semiconductor integrated circuit, as well as a program for directing a computer to execute the method.
2. Description of the Background Art
In designing semiconductor integrated circuits, there is increasing demand for improvements in the degree of integration, operation speed and power consumption of the circuits, whereas there is increasing demand for a reduction in design period. It is therefore required to improve the degree of integration, operation speed and power consumption in a short period of time.
As technique of increasing the efficiency of and automatizing the layout designs of semiconductor integrated circuits, there are, for example, a method called “layout synthesis” to generate a layout based on a net list (i.e., a connected information of transistor level), and a method called “technology migration” to generate a layout of a desired design rule by using a layout drawn under a certain design rule.
When employing these techniques, it is desirable that the channel width of each transistor is optimized in designing a circuit, in order to improve the degree of integration, operation speed and power consumption of the circuit.
Referring now to the flowchart shown in
FIG. 22
, a procedure of generating a layout according to a conventional layout generating method will be described below.
First, in step S
110
, the data of a net list stored in memory is inputted, as an input data, to an optimization processing part that optimizes channel widths.
The optimization processing part optimizes a channel width to improve operation speed and reduce power consumption (step S
111
).
Specifically, the layout area is smaller as the transistor is smaller. In terms of improvements in the degree of integration, a smaller transistor is preferred, however, its operation speed cannot be increased. Also, power consumption might increase by through current due to blunting of waveform. It is therefore necessary to increase the size of a transistor that drives the portions requiring operation speed and the locations subjected to a large blunting of waveform.
Thus, the channel width optimization means to seek a transistor that should have a large channel width, and increase its channel width.
There are a variety of methods for optimizing the channel width of a transistor. One of the methods comprises the steps of: making a net list on which channel widths are minimized; seeking a transistor most contributing to improvements in driving speed and power consumption; and changing the channel width of the transistor. The sequence of these steps is repeated until a desired driving speed is attained.
Other method comprises the steps of allocating a certain value to all of the channel widths of transistors; and performing their respective simulations to obtain a combination of channel widths that produces the best result, as an optimum value.
In any case, when performing optimization, an upper limit value (the maximum value) of the channel width is set to avoid a reduction in the degree of integration of layout. Unless the maximum value is set, by the presence of a transistor occupying a large ratio of the layout area and exerting influence on operation speed and power consumption, the size of this transistor increases infinitely, resulting in a large layout area.
Returning to
FIG. 22
, in step S
112
, the net list obtained by optimizing the channel widths is temporarily stored in memory. A layout generation processing part generates a layout based on this net list (step S
113
).
This layout is then outputted and the sequence of the layout generation processing is completed (step S
114
).
The problems of the foregoing conventional techniques will be described by referring to
FIG. 23
illustrating a buffer layout.
FIG. 23
illustrates the layout of a buffer formed by two CMOS inverters. In
FIG. 23
, an active area
21
where a P channel MOS transistor (PMOS transistor) is to be formed is disposed on the upper side, and an active area
31
where an N channel MOS transistor AMOS transistor) is to be formed is disposed on the lower side.
Gate electrodes
22
and
23
are placed in parallel on the active area
21
. The portions of the active area
21
, which locate at the side exterior in the longitudinal direction of the gate electrodes
22
and
23
, become source/drain regions. Each of the source/drain regions is connected via a plurality of contact portions to an overlying first layer metal wiring
41
. The portions of the active area
21
, which underlie the gate electrodes
22
and
23
, become channel regions.
Likewise, gate electrodes
32
and
33
are placed in parallel on the active area
31
. The portions of the active area
31
, which locate at the side exterior in the longitudinal direction of the gate electrodes
32
and
33
, become source/drain regions. Each of the sour/drain region is connected via a plurality of contact portions to the overlying first layer metal wiring
41
. The portions of the active area
31
, which underlie the gate electrodes
32
and
33
, become channel regions.
Referring to
FIG. 23
, when considering the two PMOS transistors on the active area
21
, it is found that the gate electrode
22
is shorter than the gate electrode
23
, and these electrodes have different channel widths. This is due to the connection constraint with the first layer metal wiring
41
and other wiring (not shown), by which the upper limit value of the channel widths on this circuit is determined. In general, the upper limit value of a channel width is more lowered at more complicated wiring location.
With the conventional layout generating method, the upper limit value of a channel width is set in the channel width optimization, however, this value is given as a whole. For example, an upper limit is set circuit by circuit. Actually, depending on the layout shape, the upper limit of a channel width is different transistor by transistor, as previously described. Therefore, the conventional techniques cannot accurately provide the upper limit value of a channel width at the time of optimization.
For instance, in
FIG. 23
, of the two PMOS transistors in the active area
21
, the right transistor, as viewed in the figure, has room for increasing its channel width. Of the two NMOS transistors in the active area
31
, the right transistor, as viewed in the figure, has room for increasing its channel width.
When a layout is generated setting an upper limit to a large value, the layout area is increased. On the contrary, setting the upper limit to a small value decreases the degree of freedom of optimization, which causes the degradation of optimization (i.e., a drop in operation speed and an increase in power consumption on circuit).
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a layout generating apparatus to generate a layout of a semiconductor integrated circuit comprises: a compaction processing part to perform a compaction processing for converting an inputted input layout into a layout satisfying a predetermined design rule; and a channel-width optimization processing part to optimize a channel width of a transistor forming the semiconductor integrated circuit, the compaction processing part having a channel-width maximization processing part that maximizes the channel width of the transistor without changing a layout area to generate a layout after channel-width maximization and obtain a maximum channel-width value, the channel-width optimization processing part optimizing the channel width of the transistor by using the maximum channel-width value as an upper limit value.
According to a second aspect of the invention, the layout generating apparatus of the first aspect is characterized in that the compaction processing part further has a channel-width minimization processing part that minimizes the channel width of the transistor without changing a layout area to generate a layout after channel-width mi
Dimyan Magid Y
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Smith Matthew
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