Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Patent
1999-01-04
2000-09-19
Thai, Xuan M.
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
710129, 395500, 711140, G06F 1300
Patent
active
061226912
ABSTRACT:
Cache and architectural functions within a cache controller are layered and provided with generic interfaces. Layering cache and architectural operations allows the definition of generic interfaces between controller logic and bus interface units within the controller. The generic interfaces are defined by extracting the essence of supported operations into a generic protocol. The interfaces themselves may be pulsed or held interfaces, depending on the character of the operation. Because the controller logic is isolated from the specific protocols required by a processor or bus architecture, the design may be directly transferred to new controllers for different protocols or processors by modifying the bus interface units appropriately.
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Arimilli Ravi Kumar
Dodson John Steven
Lewis Jerry Don
Williams Derek Edward
Dillon Andrew J.
International Business Machines - Corporation
Thai Xuan M.
Venglarik Daniel E.
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