Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2007-12-18
2007-12-18
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S039000, C326S047000
Reexamination Certificate
active
11193308
ABSTRACT:
An apparatus and methods for interconnecting a plurality of nanoscale programmable logic array (PLA) clusters are disclosed. The appartus allows PLA clusters to be built at nanoscale dimensions, signal restoration to occur at the nanoscale, and interconnection between PLA clusters to be performed with nanoscale wiring. The nanoscale PLA, restoration, and interconnect arrangements can be constructed without using lithographic patterning to produce the nanoscale feature sizes and wire pitches. The nanoscale interconnection of the plurality of nanoscale PLA clusters can implement any logic function or any finite state machine. The nanoscale interconnect allows Manhattan (X,Y grid) routing between arbitrary nanoscale PLA clusters. The methods teach how to interconnect nanoscale PLAs with nanoscale interconnect and how to build arbitrary logic with nanoscale feature sizes without using lithography to pattern the nanoscale features.
REFERENCES:
patent: 5349558 (1994-09-01), Cleveland et al.
patent: 6128214 (2000-10-01), Kuekes et al.
patent: 6211510 (2001-04-01), Merril et al.
patent: 6256767 (2001-07-01), Kuekes et al.
patent: 6314019 (2001-11-01), Kuekes et al.
patent: 6383784 (2002-05-01), Smith
patent: 6777982 (2004-08-01), Goldstein et al.
patent: 7073157 (2006-07-01), DeHon et al.
patent: 2002/0027819 (2002-03-01), Tomanek et al.
patent: 2002/0175390 (2002-11-01), Goldstein et al.
patent: 2003/0089899 (2003-05-01), Lieber et al.
patent: 2003/0200521 (2003-10-01), DeHon et al.
patent: 2003/0206436 (2003-11-01), Eaton, Jr. et al.
patent: 2004/0113138 (2004-06-01), DeHon et al.
patent: 2004/0113139 (2004-06-01), Dehon et al.
patent: 2005/0001918 (2005-01-01), Berezin et al.
patent: 00/73996 (2000-12-01), None
patent: 02/103753 (2002-12-01), None
patent: 03/063208 (2003-07-01), None
patent: 2004/034467 (2004-04-01), None
patent: 2004/061859 (2004-07-01), None
U.S. Appl. No. 10/853,907, filed May 25, 2004, DeHon et al.
U.S. Appl. No. 10/925,863, filed Aug. 24, 2004, DeHon.
Written Opinion of the International Searching Authority for the Corresponding PCT Application No. PCT/US2005/026772, issued Jul. 27, 2005 (6 pages).
International Written Opinion for the corresponding PCT Application No. PCT Application No. PCT/US03/01555, issued on Jun. 30, 2005 (7 pages).
Albrecht, O., et al., “construction and Use of LB Deposition Machines for Pilot Production,”Thin Solid Films, vol. 284-285, pp. 152-156 (Sep. 15, 1996).
Björk. M.T., et al., “One-Dimensional Steeplechase for Electrons Realized,”Nano Letters, vol. 2, No. 2, pp. 87-89 (2002), no month.
Brown, C.L., et al., “Introduction of [2]Catenanes Into Langmuir Films and Langmuir-Blodgett Multilayers. A Possible Strategy for Molecular Information Storage Materials,”Langmuir, vol. 16, No. 4, pp. 1924-1930 (2000), no month.
Chen, Y., et al., “Nanoscale Molecular-Switch Crossbar Circuits,”Institute of Physics Publishing, Nanotechnology 14, pp. 462-468 (2003), no month.
Chen, Y. et al., “Self-Assembled Growth of Epitaxial Erbium Disilicide Nanowires on Silicon (001),”Applied Physics Letters, vol. 76, No. 2, pp. 4004-4006 (Jun. 26, 2000).
Chou, S.Y., “Sub-10 nm Imprint Lithography and Applications,”J. Vac. Sci. Technol. B, vol. 15, No. 6, pp. 2897-2904 (Nov./Dec. 1997).
Collier, C.P., et al., “A [2]Catenane-Based Solid State Electronically Reconfigurable Switch,”Science, vol. 289, pp. 1172-1175 (Aug. 18, 2000).
Collier, C.P., et al., “Electronically Configurable Molecular-Based Logic Gates,” Science, vol. 285, pp. 391-394 (Jul. 16, 1999).
Cui, Y., et al., “Diameter-Controlled Synthesis of Single-Crystal Silicon Nanowires,”Applied Physics Letters, vol. 78, No. 15, pp. 2214-2216 (Apr. 9, 2001).
Cui, Y., et al., “Doping and Electrical Transport in Silicon Nanowires,”The Journal of Physical Chemistry, vol. 104, No. 22, pp. 5213-5216 (Jun. 8, 2000).
Cui, Y., et al., “Functional Nanoscale Electronic Devices Assembled Using Silicon Nanowire Building Blocks,”Science, vol. 291, pp. 851-853 (Feb. 2, 2001).
DeHon, A., “Array-Based Architecture for FET-Based, Nanoscale Electronics,”IEEE Transactions on Nanotechnology, vol. 2, No. 1, pp. 23-32 (Mar. 2003).
Dekker, C., “Carbon Nanotubes As Molecular Quantum Wires,”Physics Today, pp. 22-28 (May 1999).
Derycke, V., et al., “Carbon Nanotube Inter- and Intramolecular Logic Gates,”Nano Letters, vol. 1, No. 9, pp. 453-456 (Sep. 2001).
Goldstein, S.C., et al., “NanoFabrics: Spatial Computing Using Molecular Electronics,”Proc. Of The 28th Annual International Symposium on Computer Architecture, pp. 1-12 (Jun. 2001).
Gudiksen, M.S., et al., “Growth of Nanowire Superlattice Structures for Nanoscale Photonics and Electronics,”Nature, vol. 415, pp. 617-620 (Feb. 7, 2002).
Huang, Y., et al., “Directed Assembly of One-Dimensional Nanostructures Into Functional Networks,”Science, vol. 291, pp. 630-633 (Jan. 26, 2001).
Huang, Y., et al., “Logic Gates and Computation From Assembled Nanowire Building Blocks,”Science, vol. 294, pp. 1313-1317 (Nov. 9, 2001).
Lauhon, L.J., et al., “Epitaxial Core-Shell and Core-Multishell Nanowire Hetorostructures,”Nature, vol. 420, pp. 57-61 (Nov. 7, 2002).
Lieber, C.M., “Nanowire Superlattices,”Nano Letters, vol. 2, No. 2, pp. 81-82 (Feb. 2002).
Morales, A.M., et al., “A Laser Ablation Method for the Sythesis of Crystalline Semiconductor Nanowires,”Science, vol. 279, pp. 208-211 (Jan. 9, 1998).
Tans, S.J., et al., “Room-Temperature Transitor Based On A Single Carbon Nanotube,”Nature, vol. 393, pp. 49-52 (May 7, 1998).
Ulman, A., “Part Two: Langmuir-Blodgett Films,”An Introduction to Ultrathin Organic Films, Section 2.1, pp. 101-132 (1991), no month.
Whang, D., et al., “Nanolithography Using Hierarchically Assembled Nanowire Masks,”Nano Letters, vol. 3, No. 7, pp. 951-954 (2003), no month.
Wu, Y., et al., “Block-by-Block Growth of Single-Crystaline Si/SiGe Superlattice Nanowires,”Nano Letters, vol. 2, No. 2, pp. 83-86 (2002), no month.
Ziegler, M. M., ert al., “CMOS/NANO Co-Design for Crossbar-based Molecular Electronics Systems”IEEE Transactions on Nanotechnology, vol. 2, No. 4, pp. 217-230 (Dec. 4, 2004).
California Institute of Technology
Ladas & Parry LLP
Tran Anh Q.
LandOfFree
Apparatus and method of interconnecting nanoscale... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method of interconnecting nanoscale..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method of interconnecting nanoscale... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3858629