Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-12-07
2004-08-10
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090, C324S763010, C324S1540PB
Reexamination Certificate
active
06774657
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method of inspecting a semiconductor integrated circuit, and more particularly, to an inspection apparatus and method suitable for use in burn-in inspection.
2. Description of the Background Art
In order to reveal defects which would lead to initial failures, a burn-in inspection or a like inspection is performed during processes. A burn-in inspection apparatus is equipped with a burn-in board on which a plurality of semiconductor integrated circuits are to be placed. A plurality of sockets are provided on the surface of the burn-in board so that semiconductor integrated circuits can be provided on the plurality of sockets. Semiconductor integrated circuits to be connected to the corresponding sockets are electrically connected to the main unit of the inspection apparatus by way of terminals of the sockets or by way of wiring patterns provided on the burn-in board.
Sockets provided on the burn-in board must be prepared for each semiconductor integrated circuit package. In a case where semiconductor integrated circuit packages of different types must be inspected, a burn-in board must be prepared for each of the semiconductor integrated circuit packages.
Even in a case where semiconductor integrated circuit packages of the same type are inspected, if functions assigned to pins are not unified and if the packages cannot be properly inspected by means of changing settings of the main unit of the inspection apparatus, identical burn-in packages cannot be used. Therefore, in such a case, there must be prepared a burn-in board designed specifically for each of the semiconductor integrated circuits of the same package.
For example, Japanese Patent Laid-Open No. Hei 6-58987 describes a technique of making a burn-in board suitable for use with a plurality of semiconductor integrated circuits of different types. The technique is intended for enabling a single burn-in board to be used with semiconductor integrated circuits which differ from each other in terms of configuration of a power pin and a GND pin.
FIG. 10
is a perspective view showing a portion of a burn-in board described in the foregoing patent document. A plurality of sockets
3
, each receiving a semiconductor integrated circuit
2
, are provided on the surface of a burn-in board
1
(
FIG. 10
shows one of the sockets
3
). The socket
3
has socket terminals
4
corresponding to a plurality of terminals of the semiconductor integrated circuit
2
.
The burn-in board
1
has through holes corresponding to the respective socket terminals
4
. The socket
3
is placed such that the socket terminals
4
project to the underside of the burn-in board
1
. A relay pin
5
is provided on the underside of the burn-in board
1
so as to communicate with a power line pattern or a GND pattern laid on the burn-in board
1
.
An exchange board
6
is attached to the underside of the burn-in board
1
. On the surface of the exchange board
6
, there is provided a wiring pattern
9
for interconnecting the through holes (including through hole
7
) corresponding to the socket terminals
4
with a through hole
8
corresponding to the relay pin
5
, and for interconnecting a specific through hole
7
and the through hole
8
corresponding to the relay pin
5
.
The socket terminal
4
inserted into a specific through hole
7
is electrically connected to the relay pin
5
inserted in the through hole
8
, by means of the exchange board
6
being attached to the burn-in board
1
. In other words, when the exchange board
6
is attached to the burn-in board
1
, among the terminals of a semiconductor integrated circuit, a terminal corresponding to the through hole
7
is electrically connected, by way of the exchange board
6
, to a power line pattern or a GND pattern provided on the burn-in board. Accordingly, the structure of the burn-in board
1
shown in
FIG. 10
enables use of a single burn-in board with semiconductor integrated circuits
2
of different types having different configurations of a power pin or a GND pin, by means of appropriately replacing the exchange board
6
.
A burn-in inspection apparatus having the function of inspecting a semiconductor integrated circuit has recently been used. Such an inspection apparatus is required to establish an electrical connection between a signal pin of the semiconductor integrated circuit and the burn-in inspection apparatus, as well as between the burn-in inspection apparatus and a power pin or a GND pin of a semiconductor integrated circuit. In a case where a plurality of semiconductor integrated circuits have different signal pin configurations, a burn-in board must take care a difference in signal pin configuration between the semiconductor integrated circuits.
FIGS. 11A and 11B
are illustrations for describing cases where the conventional technique is used for inspecting two semiconductor integrated ICs
1
and
2
, which differs from each other in terms of configuration of a power pin, a GND pin, and signal pins. For the sake of brevity, the burn-in board
1
and the socket
3
are omitted from these drawings.
In the cases shown in
FIGS. 11A and 11B
, through holes
8
are formed so as to correspond to all terminals of the ICs
1
and
2
. All the terminals of the IC
1
are electrically connected, by way of an exchange board
6
A, to the wiring pattern laid on the burn-in board
1
. Further, all the terminals of the IC
2
are electrically connected, by way of an exchange board
6
B, to the wiring pattern laid on the burn-in board
1
. In this case, there may be a case where the exchange boards
6
A and
6
B are required to assume complicated wiring structures in order to achieve desired electrical connections. In these examples, as shown in
FIG. 11B
, the exchange board
6
B requires complicated cross wiring.
The cross wiring such as that shown in
FIG. 11B
can be achieved by means of forming the exchange board
6
B in the form of a multi-layer wiring board, or by stacking a plurality of single layers in the form of the exchange board
6
B. However, use of a multi-layer wiring board or stacking of single layers cancels benefits which would be yielded by rendering the burn-in board
1
versatile. Thus, the practical significance of realization of a versatile burn-in board is lessened.
The previously described conventional technique requires formation of through holes for the socket terminals
4
in the burn-in board
1
and placing the relay pin
5
in the socket
3
. Thus, according to the conventional technique, each of the semiconductor integrated circuits requires on the burn-in board
1
a large occupational area. As a result, the number of semiconductor integrated circuits which can be mounted on a single burn-in board is decreased.
According to the conventional technique, through holes are formed in the burn-in board
1
specifically for each socket
3
. Accordingly, a single burn-in board
1
cannot be used commonly for a plurality of sockets. Thus, a single burn-in board
1
cannot be used by a wide range of semiconductor integrated circuits.
In addition to the foregoing problem, the conventional technique encounters a problem of difficulty in using a single burn-in board for semiconductor integrated circuits of different word-bit configurations. Alternatively, it becomes difficult to ensure a space for a bypass capacitor for eliminating noise arising in a power line pattern or a GND pattern or the like.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the foregoing drawbacks of the background art and is aimed at providing a highly-versatile inspection apparatus which can be used with various types of semiconductor integrated circuits.
The present invention is also aimed at providing a method of inspecting a semiconductor integrated circuit using an inspection apparatus having the foregoing characteristics.
The above objects of the present invention are achieved by an inspection apparatus for inspecting a plurality of semiconductor integrat
Hashimoto Osamu
Tanimura Masaaki
McDermott & Will & Emery
Nguyen Jimmy
Renesas Technology Corp.
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