Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2003-01-14
2004-12-28
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S206000, C365S210130
Reexamination Certificate
active
06836443
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor memories, and more particularly to a high-speed sensing system for low voltage memories.
BACKGROUND OF THE INVENTION
Various types of memory devices, such as random access memory (RAM), read-only memory (ROM) and non-volatile memory (NVM), are known in the art. A memory device includes an array of memory cells and peripheral supporting systems for managing, programming and data retrieval operations.
Each of the memory cells in a memory device can be configured to provide an electrical output signal during a read operation. A sense amplifier is coupled to receive the electrical output signal, and in response, provide a data output signal representative of the logic state of the data stored by the memory cell.
In general, sense amplifiers determine the logical value stored in a memory cell by comparing the electrical output signal (i.e., voltage or current) provided by the cell with a threshold value (i.e., voltage or current). If the electrical output signal exceeds the threshold value, the sense amplifier provides a data output signal having a first logic value (e.g., logic “1”), thereby indicating that the memory cell is in a first logic state (e.g., an erased state). Conversely, if the electrical output signal is less than the threshold value, the sense amplifier provides a data output signal having a second logic value (e.g., logic “0”), thereby indicating that the memory cell is in a second logic state (e.g., a programmed state).
The threshold value is typically set at a level that is between the expected electrical output signal for a programmed state of a memory cell and the expected electrical output signal for an erased state of a memory cell. It is desirable to set the threshold value at a level that is sufficiently far from both expected levels, so that noise on the electrical output signal will not cause false results.
FIG. 1
is a block diagram of a conventional memory device
100
, which includes memory array
110
, reference memory array
112
, clamping circuits
120
-
121
, sense amplifier first stages
130
-
131
, and sense amplifier second stage
140
. Memory array
110
and reference memory array
112
each include a plurality of non-volatile memory cells arranged in rows and columns. For example, memory array
100
includes non-volatile memory cell
111
, and reference memory array
112
includes non-volatile memory cell
113
. Clamping circuit
120
includes PMOS transistors P
1
-P
2
, NMOS transistor N
1
and comparator C
1
, which are connected as illustrated. Similarly, clamping circuit
121
includes PMOS transistors P
7
-P
8
, NMOS transistor N
2
, and comparator C
2
, which are connected as illustrated. Clamping circuits
120
and
121
cause the charging operation to be performed in a staged manner to improve the efficiency of the sensing operation. Sense amplifier first stage
130
includes PMOS transistor P
3
and NMOS transistor N
4
. Sense amplifier first stage
131
includes PMOS transistor P
6
and NMOS transistor N
3
. Sense amplifier second stage
140
includes PMOS transistors P
4
-P
5
, and current comparator circuit
141
.
To read (or “sense”) the state of a memory cell in memory array
110
, the word line and bit lines associated with the memory cell are selected. For example, to read memory cell
111
, a read voltage is applied to word line W
1
by a row decoder, while bit line B
N
is coupled to a system bit line BL by a column decoder, and bit line B
N+1
is grounded. A corresponding reference memory cell
113
in reference array
112
is configured in a similar manner. Thus, a read voltage is applied to word line W
1
by a row decoder, while bit line B
M
is coupled to a reference bit line BL_REF by a column decoder, and bit line B
M+1
is grounded. System bit line BL and reference bit line BL_REF exhibit capacitances C
BL
and C
REF
—
BL
, respectively.
Sense amplifier first stage
130
and clamping circuit
120
apply a sense voltage on system bit line BL, thereby causing a read current I
BL
to flow through memory cell
111
. The magnitude of the read current I
BL
is determined by the logic state of memory cell
111
(i.e., programmed or erased). This read current I
BL
is mirrored to PMOS transistor P
4
of sense amplifier second stage
140
.
Similarly, sense amplifier first stage
131
and clamping circuit
121
apply the sense voltage on reference bit line BL_REF, thereby causing a read current I
BL
—
REF
to flow through reference memory cell
113
. The magnitude of the read current I
BL
—
REF
is determined by the logic state of reference memory cell
113
. Reference memory cell
113
is programmed such that the magnitude of the read current I
BL
—
REF
is less than the magnitude of the read current I
BL
when memory cell
111
is programmed, and greater than the magnitude of the read current I
BL
when memory cell
111
is erased. The read current I
BL
—
REF
is mirrored to PMOS transistor P
5
of sense amplifier second stage
140
.
After the read currents I
BL
and I
BL
—
REF
have had time to develop, the enable signal EN is activated, thereby causing comparator circuit
141
to detect the difference between these read currents. In response, comparator circuit
141
provides an output data signal D
OUT
, representative of the data stored in memory cell
111
.
Memory device
100
is described in more detail in commonly owned, co-pending U.S. patent application Ser. No. 09/935,013, “Structure and Method for High Speed Sensing of Memory Arrays”, by Alexander Kushnarenko and Oleg Dadashev [TSL-103].
Memory device
100
will not operate properly unless the V
DD
supply voltage is greater than a minimum voltage V
DD
—
MIN
, which is defined as follows.
V
DD
—
MIN
=V
DIODE
—
MAX
+V
BL
—
MIN
+V
P1/P8
+V
P2/P7
(1)
In Equation (1), V
DIODE
—
MAX
is the maximum voltage drop across PMOS transistor P
3
or PMOS transistor P
6
, V
BL
—
MIN
is the minimum acceptable bit line voltage for the non-volatile memory technology, V
P1/P8
is the drain-to-source voltage drop of PMOS transistor P
1
(or PMOS transistor P
8
), and V
P2/P7
is equal to the drain-to-source voltage drop on PMOS transistor P
2
(or PMOS transistor P
7
).
For example, if V
DIODE
—
MAX
is equal to 1.0 Volt, V
BL
—
MIN
is equal to 1.8 Volts, and V
P1/P8
and V
P2/P7
are equal to 0.05 Volts, then the minimum supply voltage V
DD
—
MIN
is equal to 2.9 Volts (1.8V+1V+0.05V+0.05V). In such a case, memory device
100
would not be usable in applications that use a V
DD
supply voltage lower than 2.9 Volts.
In addition, sense amplifier first stages
130
and
131
are sensitive to noise in the V
DD
supply voltage. If, during a read operation, the V
DD
supply voltage rises to an increased voltage of V
DD
—
OVERSHOOT
, then the voltages V
SA1
and V
SA2
on the drains of PMOS transistors P
3
and P
6
rise to a level approximately equal to V
DD
—
OVERSHOOT
minus a diode voltage drop. If the V
DD
supply voltage then falls to a reduced voltage of V
DD
—
UNDERSHOOT
, then transistors P
3
and P
6
may be turned off. At this time, sense amplifier first stages
130
and
131
cannot operate until the voltages V
SA1
and V
SA2
are discharged by the cell currents I
BL
and I
BL
—
REF
. If the cell current I
BL
is low, then sense amplifier first stage
130
will remain turned off until the end of the read operation, thereby causing the read operation to fail.
Accordingly, it is desirable to provide a sensing system that can accommodate low supply voltages and tolerate supply voltage fluctuations.
SUMMARY OF THE INVENTION
The present invention provides a system and method for sensing the state of a memory cell by integrating current differences between a read current produced by the memory cell and a reference current produced by a reference memory cell. The integration process generates differential measurement voltages that can be compared to determine the state of the memory cell relative to the state of the reference memory cell. By
Hoffman E. Eric
Nguyen Van Thu
Tower Semiconductor Ltd.
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