Apparatus and method of compensating for phase delay in...

Details Apparatus and method of compensating for phase delay in... Apparatus and method of compensating for phase delay in...

2005-02-22

2005-02-22

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S191000, C365S233100, C365S189050, C327S276000, C327S278000, C327S281000, C327S161000

Reexamination Certificate

active

06859404

ABSTRACT:
An apparatus for minimizing a skew occurring due to a change of data pattern by previously recognizing data pattern before data is outputted from the semiconductor device. The apparatus of compensating for a phase delay in a semiconductor device having a delay locked loop (DLL) for generating DLL clock includes: a data pattern detection block for detecting patterns of data loaded on data line and determining delay compensation amount of the data inputted to data output driver based on the detected data patterns; and a delay compensation block for compensating for phase delay of clock relating to the DLL clock inputted to the data output driver under a control of an output signal of the data pattern detection block.

REFERENCES:
patent: 5117135 (1992-05-01), Lee et al.
patent: 6473455 (2002-10-01), Kwon
patent: 6549052 (2003-04-01), Okayasu

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