Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2005-01-18
2005-01-18
Fleming, Fritz (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S053000, C710S056000, C710S057000, C710S018000, C710S019000, C710S029000, C341S097000, C341S098000, C377S034000
Reexamination Certificate
active
06845414
ABSTRACT:
An apparatus and method for controlling an asynchronous First-In-First-Out (FIFO) memory. The asynchronous FIFO has separate, free running read and write clocks. A number of n-bit circular Gray code counters are used to handshake the operation between read and write parts of the FIFO, wherein n is any integer more than one. Additional binary counters are used to accumulate the read and write overflows for the circular Gray code counters. When any circular Gray code counter is overflow, the read or write count is transferred to the respective binary counter for recording the FIFO accesses.
REFERENCES:
patent: 5084841 (1992-01-01), Williams et al.
patent: 5426756 (1995-06-01), Shyi et al.
patent: 5790891 (1998-08-01), Solt et al.
patent: 6337893 (2002-01-01), Pontius
patent: 6434642 (2002-08-01), Camilleri et al.
patent: 6553448 (2003-04-01), Mannion
patent: 6703950 (2004-03-01), Yi
patent: 6718449 (2004-04-01), Phi
Hsu Fu-Chou
Yeh Kuo-Wei
Fleming Fritz
Merchant & Gould P.C.
Nguyen Tanh Q
Silicon Integrated Systems Corp.
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