Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-15
2001-10-30
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S685000, C438S654000, C438S655000, C438S658000
Reexamination Certificate
active
06309966
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the fabrication of semiconductor devices; and, more particularly, to a method of achieving superior via fill.
BACKGROUND OF THE INVENTION
As the semiconductor industry continues to increase the density of devices manufacturable on a semiconductor substrate, the device features continue to shrink below the quarter-micron size. The critical dimensions of vias between different metal layers are decreased, making it more difficult to achieve void-free via fill as the stringent restrictions on the pitch and space results in straight-walled vias with high aspect ratios. The problem of having voids become apparent after a chemical mechanical planarization (CMP) step followed by a subsequent wet chemical cleaning step. The voids can potentially open up a pathway for fluids to become entrapped within the via.
A tungsten via fill process that is commonly known to those skilled in the art typically consists of two important film deposition steps. The two film deposition steps include a nucleation step and a bulk film deposition step. The nucleation step is typically associated with poor step coverage, which may eventually lead to voiding (due to premature closure of the via) and increased surface roughness. Further, the nucleation step is unstable with a commonly known process having a 1:1 gas flow rate ratio of tungsten hexafluoride (WF
6
) and silane (SiH
4
) at a certain pressure regimes, such as approximately 20 to 40 torr. Within this regime, the nucleation step is sensitive to the precision of the actual gas flow rates, especially during the initial stages of nucleation. Mass flow controllers (MFCs), are used to regulate the gas flow rate for a silane gas source and a tungsten gas source. The response times of the MFCs affect the nucleation film. For example, if the MFC for the tungsten gas source responds quicker than the MFC from the silane gas source, the film exhibits localized thinning near the center of the wafer. The currently known process, as a result, requires precise adjustment of the MFCs to achieve accurate gas flow rates. Further, a process with a pressure such as 30 torr, is more susceptible to gas phase nucleation (GPN).
Prior to the tungsten via fill process, a titanium nitride (TiN) film is reactively sputtered on the via sidewalls to act as a “glue” liner for the tungsten via fill. Alternative methods to deposit the “glue” liner include chemical vapor deposition or a combination of chemical and physical vapor deposition. The mechanism of the sputtering process is generally a line-of-sight process; therefore, the top area of the via is exposed more to the reactive species than the bottom of the via. The resulting profile includes an “overhang” at the top of the via as illustrated in
FIG. 1. A
via
100
comprises two sidewalls
102
and a TiN liner
103
with an “overhang”
104
. The overhang
104
affects the nucleation film as the depositing tungsten generally grows away from the surface. In other words, the tungsten nucleation film growth is in a direction perpendicular to the surface of the sidewalls. As a result, the tungsten nucleation film will grow conforming to the existing overhang
104
from the TiN liner
103
and the top area of the via will close prematurely, creating a void.
The uniformity of a deposited film in patterned features like a trench or a via (such as the TiN liner
103
) is referred to as “step coverage”. The step coverage is typically determined by taking a ratio of the maximum thickness and the minimum thickness and converting the value to a percentage. By way of example, a 60% step coverage of the TiN liner
103
may indicate a maximum thickness of about 10 nanometers (nm) at the top of a via and a minimum thickness of about 6 nm at the bottom of the via sidewall. Ideally, the goal is to have 100% step coverage for a TiN liner deposition. As straight-sidewalls and high aspect ratios of the vias accompany the decreasing dimensions of integrated circuits, the problem of the step coverage for a TiN liner, such as the TiN liner
103
of
FIG. 1
, is increased. Substantial thinning of a TiN liner near the bottom of via sidewall is evident and illustrated with the TiN liner
103
of FIG.
1
. The poor step coverage in the TiN liner
103
, in turn, results in poor step coverage of the tungsten nucleation film. It is also conceivable that non-uniformity during the via etch process can result in areas without any liner coverage. The absence of any liner coverage reduces the growth rate of the tungsten nucleation film.
Solutions to resolve the voiding problem include varying the tungsten film chemistry, the tungsten nucleation film thickness, and the TiN liner thickness. The TiN liner thickness in comparison with the tungsten nucleation film thickness, however, is almost negligible. Typically, the liner thickness is about 10 nm and the tungsten nucleation film thickness is about 100 nm. The overhang profile created during the TiN liner deposition, therefore, is more pronounced after forming the tungsten nucleation film. By increasing the tungsten nucleation film thickness, the step coverage becomes worse as the overhang profile from the TiN liner is more pronounced. Depositing a tungsten nucleation film with a thickness that is too thin, on the other hand, forms a by-product called hydrogen fluoride (HF) which attacks the TiN liner and creates defects known as “woil holes” that results when the WF
6
gas contacts the silicon. It is desired to fabricate semiconductor devices using reliable and robust processing methods to improve the tungsten fill characteristics for vias with high aspect ratios as the device structures continue to scale down below the quarter micron size.
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Riley and Clark, “Integrated chemical vapor deposition and plasma etchback of tungsten in a multichamber, single-wafer system,”J. Electrochem. Soc., 138(10):3008-3013, Oct. 1991.
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Ciancio Anthony
Govindarajan Shrinivas
Akin Gump Strauss Hauer & Feld L.L.P.
Dang Trung
Motorola Inc.
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