Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-09-03
2001-04-10
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S100000, C711S218000
Reexamination Certificate
active
06216193
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to network interfaces, and more specifically to arrangements in network interfaces for loading data for transfer, using Direct Memory Access (DMA) techniques, via a host bus between a host memory and the network interface.
2. Background Art
Network interfaces connecting a host computer to a network such as an Ethernet-type or 802.3 network, typically utilize a host bus to transfer information between a host memory and the network interface. Two types of bus transfers may be used, namely master mode and slave mode. In master mode, a transaction or transfer of information over the bus is initiated by the network interface as a master, which arbitrates for use of the bus along with other masters requesting use of the bus. One example of a host bus is the peripheral component interconnect (PCI) local bus. A single transaction or transfer of information over a PCI bus comprises an address phase followed by one or more contiguous data phases. In conducting transactions, the PCI bus makes use of a centralized, synchronous arbitration scheme in which each PCI master must arbitrate for each transaction the master wishes to perform using a unique request and grant signal. These signal lines are attached to a central arbiter and a request-grant handshake is used to grant the master access to the bus. A common sequence for a request-grant handshake is begun when the master asserts a request signal to request use of the bus. Typically, a host CPU will respond with a grant signal which is followed the by assertion of a frame signal that together identify when the bus is available for use by the network interface.
During a PCI data burst transfer between a network interface and a host memory, signals are exchanged and data is transferred during a time when a number of other activities may be occurring internal to the network interface, the host memory, or other requesting components linked to the PCI bus. Complex bus termination conditions are events that forcibly halt PCI bus data transfer, and may be caused by different events. Two examples of complex conditions include when a host memory is not ready to receive a data transfer after the bus has been secured, or when the host memory becomes unable to continue receiving data following initiation of the data transfer. In either case, the target asserts a STOP# signal on the PCI bus to terminate the data transfer. In response to these exemplary events, network interfaces transferring data onto the PCI bus enter a RETRY or DISCONNECT state.
The events or conditions that initiate a DISCONNECT state include when the target memory (i.e., the host memory) is slow to complete the data phase, the target memory does not support the data burst mode, the target memory does not understand the addressing sequence, the current data item crosses over an address boundary of the target memory, or a data burst memory transfer crosses over a cache line boundary. The events or conditions that initiate a RETRY state include when the target memory is very slow to complete the first data phase, there is a snoop hit on a modified cache line, a resource of the target is busy, or the target memory is locked. When any of these conditions causing DISCONNECT or RETRY occur, the target may use a stop signal (STOP#) to tell the initiator to end the transaction on the current data phase. By using a device select signal (DEVSEL#) and a target ready signal (TRDY#) in conjunction with the stop signal (STOP#), the target can indicate to the initiator to disconnect, retry, or enter other complex bus termination conditions.
Assuming, in a DMA access mode, the master decides to resume the data burst transfer, the master then re-arbitrates for bus ownership. When the master successfully re-acquires PCI bus ownership, the initiator re-initiates the transaction using the double word address of the next data item that would have been transferred if the complex condition (e.g., disconnection) had not occurred. In other words, the initiator resumes the transfer where it left off.
In prior art systems data was frequently lost upon entry of recovery from these states because data transferred during the occurrence of a complex bus termination condition would be lost. Prior art systems using FIFO (first-in, firstout) buffer memory that output data in response to a data transfer request would lose the data if the transfer was not successful. Hence, complicated recovery arrangements were made in prior art systems to mitigate the loss of data or accommodate for the complex termination conditions, and typically required use of an equally complicated reset protocol. For example, higher network protocol layers would send a message across the network, requesting the transmitting station to resend a data pocket Hence, network throughput would be reduced due to resent packets.
SUMMARY OF THE INVENTION
There is a need for an arrangement that accommodates for complex host bus termination conditions during transfers of data between a network interface device and a target memory via the host bus.
There is also a need for an arrangement that enables data to be transferred reliably between a network interface device and a target memory via a host bus by reading the data from a random access memory. Specifically, there is a need for reliably transferring data from a network interface device to a target memory despite the occurrence of complex bus termination conditions, by selectively addressing a random access memory storing the data.
There is also a need for an arrangement that outputs data from a random access buffer memory in a network interface to a host memory via a host bus in response to complex bus termination conditions by resupplying data which was not successfully received by the host memory.
There is also a need for an arrangement in a network interface that selectively supplies address data to a random access buffer memory based on the determination of whether data, supplied from the random access memory to a target host memory via a local bus, has been successfully received by the target host memory.
These and other needs are attained by the present invention, where a random access memory is selectively addressed with either a read address or a reload address based on successful transfer of data. The reload address differs from the read address by up to a predetermined burst value, and is incremented based on successful transfer of data to the target If previously supplied data has not been successfully received by the target, the reload address is supplied to the random access memory so that the next data, following the last successfully received data, is re-supplied from the memory to the target.
According to one aspect of the present invention, a method in a network interface having a bus access controller is configured for transferring frame data between a target via a host bus. The method comprises storing a read address in an address register and a reload address in a reload register, where the read address and the reload address each identify a corresponding data word stored in a random access memory and the reload address differs from the read address up to a predetermined data burst value. The data word identified by the read address is output from the random access memory to a holding register array having a number of successive holding registers, one of the holding registers being an output holding register. The read address in the address register is incremented based on the output holding register outputting the data word onto the host bus. The reload address is selectively supplied to the random access memory based on unsuccessful reception of the output data word by the target The selective supplying of the reload address to the random access memory allows data to be reloaded to the holding register array if the target was unable to receive data previously transmitted Thus, data previously output from the random access memory during a PCI burst transfer having encountered complex
Chiang John M.
Kuo Jerry Chun-Jen
Lai Po-Shen
Niu Autumn Jane
Advanced Micro Devices , Inc.
Ray Gopal C.
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