Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1997-12-18
2000-05-09
Thai, Tuan V.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711129, 711153, 370452, G06F 1200
Patent
active
060617675
ABSTRACT:
A network interface device having a random access memory for buffering data between a host bus interface and a media access controller includes a buffer controller configured for storing a data frame in combination with tracking and status information associated with the storage of the data frame. The memory controller is configured for writing receive frame data received from a media access controller into the random access memory. The tracking and status information is stored in memory locations contiguous with the data frame to enable a read controller operating in a separate clock domain to access the status information and the corresponding data frame as a single data unit. Moreover, the disclosed embodiment stores the status information at the beginning of the stored data unit, enabling a controller reading the buffer memory to immediately determine the status of the corresponding stored data frame.
REFERENCES:
patent: 4914652 (1990-04-01), Nguyen
patent: 5802546 (1998-09-01), Chisholm et al.
patent: 5860119 (1999-01-01), Dockser
Kuo Jerry Chun-Jen
Lai Po-Shen
Niu Autumn Jane
Advanced Micro Devices , Inc.
Moazzami Nasser
Thai Tuan V.
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