Apparatus and method implementing repairs on a memory device

Details Apparatus and method implementing repairs on a memory device Apparatus and method implementing repairs on a memory device

1999-08-23

2000-11-07

Wright, Norman M.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 8, 714769, H02H 305, G11C 2900

Patent

active

061450928

ABSTRACT:
An on-chip testing device separately locates must-repairs or preferred-repairs in a row direction and column direction of a memory array. A row counter and a column counter are operated to index the memory array in row-major order, and then in column-major order (or vice versa). A running total of the number of failures is kept for each row and column, when the running total equals or exceeds a predetermined value, the row or column is determined to be a must-repair or a preferred repair. Rows to be repaired are substituted with redundant memory rows and-columns-to be prepared are substituted with redundant memory columns.

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