Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-02-28
2008-10-28
Myers, Paul R (Department: 2111)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07444472
ABSTRACT:
A microprocessor including processor logic and sparse write logic. The processor logic asserts address and request signals to provide an address and a request for a cache line memory write transaction. The sparse write logic causes the processor logic to modify a second part of the write request to specify the sparse write command value and to provide the corresponding enable bits. The sparse write-combined memory write transaction may be a quad-pumped cache line write transaction for writing eight quadwords in which each enable bit identifies a corresponding doubleword. A method of performing a sparse write-combined write transaction including providing an address and a request for a memory write transaction, indicating that the memory write transaction is a sparse write-combined write transaction, asserting enable signals for the sparse write-combined write transaction, and providing data for the sparse write-combined write transaction.
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“Microarchitecture and performance analysis of a SPARC-V9 microprocessor for enterprise server systems” by Sakamoto et al. (abstract only) Publication Date: Feb. 8-12, 2003.
Huffman James W.
Huffman Richard K.
Myers Paul R
Stanford Gary R.
Via Technologies Inc.
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