Apparatus and method for write miss processing in a copy-back da

Details Apparatus and method for write miss processing in a copy-back da Apparatus and method for write miss processing in a copy-back da

1997-06-27

1999-07-06

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711135, 711137, 711140, 711154, 711158, 711126, G06F 1200

Patent

active

059208899

ABSTRACT:
An apparatus for processing a write miss signal from a copy-back data cache includes a load-store unit with an allocating load buffer, a non-allocating store buffer, and a priority control circuit to generate write-after-read hazards and read-after-write hazards to preserve the processing priority of entries within the allocating load buffer and the non-allocating store buffer. A prefetch circuit enqueues a prefetch command in the allocating load buffer and a store command in the non-allocating store buffer upon a write miss to the copy-back data cache. Thus, the priority control circuit forces a write-after-read hazard on the store command in the non-allocating store buffer. As a result, the prefetch command in the allocating load buffer secures an allocated line in the copy-back data cache, allowing the store command of the non-allocating store buffer to write data to the allocated line.

REFERENCES:
patent: 5197144 (1993-03-01), Edenfield et al.
patent: 5761712 (1998-06-01), Tran et al.
patent: 5809530 (1998-09-01), Samra et al.
patent: 5848433 (1998-12-01), Tran et al.
Chen and Baer, "A Performance Study of Software and Hardware Data Prefetching Schemes", Proceedings of the IEEE, pp. 223-232 (1994).

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