Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2001-08-08
2004-09-21
Fleming, Fritz (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S005000, C710S015000
Reexamination Certificate
active
06795879
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to digital signal processing units and, more particularly, to the wait (or stall) state of the central processing unit. In a wait state, the execution unit of the central processing unit is temporarily inactivated. The present invention provides apparatus and a technique for recording the occurrence of a wait state and identifying the origin of the wait state.
2. Background of the Invention
In order to provide the maximum computational power, a central processing unit should maintain, as nearly as is possible, uninterrupted processing of an instruction stream by the execution unit. Any interruption of the central processing unit, typically referred to a central processing unit stall (state) or wait (state), results in a lowered efficiency and increased program execution time. As a practical matter, several conditions can occur which result in a stall or wait state for the execution unit. When the origin of a stall condition is known, steps can be taken to minimize the probability of the occurrence of condition. Such steps can include the modification of the program to anticipate the condition that produces the stall state.
Typically, the execution unit has a plurality of READY (RDY) signals applied thereto. The READY signals indicate the status of associated apparatus that provide the execution unit with data required for execution of an instruction. When all of the READY signals have a logic state that indicate the associated apparatus is in a condition to complete the execution of an instruction, the execution unit will execute the instruction. However, if one or more or the READY signals do not have the appropriate logic state, the execution unit will wait (stall) until the appropriate logic states are present for all READY signals. Only when all the READY signal lines have the appropriate logic state signals applied thereto will the execution unit begin operation. By way of specific example, the data processing system typically has memory hierarchy. The signal groups having a high probability of being required by the central processing unit are stored in relatively fast (and consequently relatively expensive) memory units typically referred to as cache memory units. The central processing unit will typically attempt to retrieve a required data from the cache memory unit. When the required data is in the cache memory unit, then the instruction sequence can be processed without interruption. However, when the required data is not in the cache memory unit, the required data must be retrieved from a memory location lower in the memory hierarchy. Being lower in the memory hierarchy, additional time will be required to retrieve the required data. When the required data is not found in the cache memory unit, a READY signal having the logic state indicating a cache miss is applied to the execution unit. In the presence of a READY signal indicating a cache miss, the execution unit will enter a stall state until the data is available and the READY signal changes state.
Because of the importance of continuous instruction execution to the efficiency of the data processing system, it would be desirable to relate the occurrence of the wait state to a portion of a software program. It would further be desirable not only to identify the presence of a wait state, but also the reason for the wait state. In the example of the cache miss cited above, the placement and/or sequence of signal groups within a program can altered to enhance the availability of the signal groups when required.
A need has therefore been felt for apparatus and an associated method having the feature that a stall or wait state of the execution unit of a central processing unit is identified. It would be yet a further feature of the apparatus and associated method to provide a record indicating the clock cycles during which the execution unit of the central processing unit was in a wait or stall state. It would be yet another feature of the apparatus and associated method to provide a record identifying the origin of the stall or wait state. It would be yet another feature of the apparatus and associated method to determine which portion of the program resulted in the stall or wait state.
SUMMARY OF THE INVENTION
The aforementioned and other features are obtained, according to the present invention, by coupling a plurality of conductors to selected portions of the central processing unit. The portions of the central processing unit to which the conductors are coupled are selected to provide a logic “0” signal to the execution unit when the central processing unit experiences a stall or wait condition. Each of these plurality of conductors is coupled to an input terminal of a logic “AND” gate. When a stall or wait condition is not present, all of the signals applied to input terminals of the logic “AND” gate are logic “1” signals and a logic “1” signal is applied to the output terminal of the logic “AND” gate. When a stall condition is present, at least one of the pluralities of conducting leads is a logic “0”, the output signal of the logic “AND” gate is a logic “0”. By storing the logic signal at the output terminal of the logic “AND” gate during each clock cycle, a record can be obtained that designates when a wait state occurred in the central processing unit. In addition to being applied to the input terminals of the logic “AND” gate, the plurality of conducting leads are applied to the input terminals of a stall analyzer unit. In the stall analyzer unit, an indicia of the origin of each stall condition identified by a logic “0” signal of a conducting lead is applied to output terminals of stall analyzer unit. The indicia of the stall condition are stored in a memory unit. According to one embodiment, one indicia is stored for each stall condition even when the stall condition extends over more than one clock cycle. When more than one condition is present in the central processing unit that results in a stall condition, a priority circuit is provided such that the indicia for the stall condition that causes a stall for the largest number of consecutive clock cycles is recorded.
REFERENCES:
patent: 3891974 (1975-06-01), Coulter et al.
patent: 5450586 (1995-09-01), Kuzara et al.
patent: 5513372 (1996-04-01), Ong et al.
patent: 5752048 (1998-05-01), Antol et al.
patent: 5928355 (1999-07-01), Petolino, Jr.
Brady W. James
Chen Alan
Fleming Fritz
Holloway William W.
Telecky , Jr. Frederick J.
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