Apparatus and method for wafer level fabrication of high...

Semiconductor device manufacturing: process – Making passive device

Reexamination Certificate

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C257S531000, C257SE21022

Reexamination Certificate

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07829425

ABSTRACT:
An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.

REFERENCES:
patent: 5204809 (1993-04-01), Andersen
patent: 5355301 (1994-10-01), Saito et al.
patent: 5541135 (1996-07-01), Pfeifer et al.
patent: 5869148 (1999-02-01), Silverscholtz et al.
patent: 6166422 (2000-12-01), Qian et al.
patent: 6249039 (2001-06-01), Harvey et al.
patent: 6462976 (2002-10-01), Olejniczak et al.
patent: 6867903 (2005-03-01), Imajuku et al.
patent: 6940147 (2005-09-01), Crawford et al.
patent: 7232733 (2007-06-01), Lotfi et al.
patent: 2002/0097129 (2002-07-01), Johnson
patent: 2003/0005569 (2003-01-01), Hiatt et al.
patent: 2004/0263310 (2004-12-01), Ding et al.
patent: 2008/0001699 (2008-01-01), Gardner et al.
Office Action from U.S. Appl. No. 11/495,143, dated Dec. 20, 2007.
Johnson et al., U.S. Appl. No. 11/274,932 entitled “Apparatus and Method for Fabricating High Value Inductors on Semiconductor Integrated Circuits” filed Nov. 14, 2005.
Hopper et al., U.S. Appl. No. 11/041,658 entitled “Integrated Switching Voltage Regulator Using Copper Process Technology” filed Jan. 24, 2005.
U.S. Appl. No. 10/658,433 entitled “High Density Integrated Inductor with Core” filed Sep. 8, 2003.
Hwang et al., U.S. Appl. No. 11/111,660, “Patterned Magnetic Layer On-Chip Inductor” filed Apr. 21, 2005.
Johnson et al., U.S. Appl. No. 11/137,767 entitled Method of Improving On-Chip Power Inductor Performance in DC-DC Regulators filed May 25, 2005.
Hopper et al., U.S. Appl. No. 11/495,143 entitled “Apparatus and Method for Wafer Level Fabrication of High Value Inductors on Semiconductor Integrated Circuits” filed Jul. 27, 2006.
“The Concise Colour Science Dictionary”, Ofxord University Press, 1997, p. 708.
Final Office Action from U.S. Appl. No. 11/495,143 dated May 29, 2008.
Office Action from U.S. Appl. No. 11/495,143 dated Aug. 15, 2008.
Office Action dated Apr. 23, 2009 in U.S. Appl. No. 11/495,143.
Office Action dated Jul. 22, 2010 in U.S. Appl. No. 12/624,259.

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